Abstract: A wafer processing method includes a holding step of holding a wafer on a chuck table; a dressing step of cutting a peripheral marginal area of the wafer by a cutting blade mounted to a cutting unit to condition a state of a cutting edge; and a dividing step of cutting streets by the cutting blade mounted to the cutting unit to divide the wafer into individual device chips.

Abstract: A method for the computer-aided optimization of tool transports for at least one tool magazine having a number of magazine locations, which is used for a machine tool for the production of one or more workpieces with the aid of the tools provided by a magazine device at a provision location, the method including: a) detecting a quantity of tools, b) determining the space required for each tool, c) detecting a quantity of occupiable magazine locations for each tool, d) detecting a permissible output magazine occupancy e) detecting the permissible target magazine occupancy, f) detecting a quantity of transport durations required for a journey of the magazine device, g) determining a partial quantity of tool transports for which a transport sequence is specifiable so that the tools are movable in the transport sequence, h) optimizing the transport sequence for the partial quantity of tool transports.

Abstract: Techniques to apply machine learning to schedule events of interest for a device user. As described herein, a typical device user is inundated with information suggesting activities and other things to do. Using these techniques, the information is categorized according to the activity and those activities that are most likely to be engaged in by the device user are recommended to the device user (via their device) as events of interest. If the device user selects an event of interest, the device is updated to reflect that selection. For instance, a calendar application may be updated to include an event description at the event's date and time. Other embodiments are described and claimed.

Abstract: A system and method for processing third party behavioral assessments that receives data for a first and second behavioral assessment, the first behavioral assessment assessing a first behavioral characteristic of a first person and the second behavioral assessment assessing a second behavioral characteristic of the first person; utilizes the first and second behavioral characteristics to calculate a behavioral parameter for the first person; compares the behavioral parameter against corresponding behavioral parameters for respective persons for a team; provides a user interface to a user device that is configured to receive a team dynamic selection; receives a hypothetical scenario dataset that describes how the first person would work with the respective persons of the team; determines an impact of including the first person in the team, based on the desired dynamic for the team and the hypothetical scenario dataset; and displays the impact via the user interface.

Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

Abstract: Compliance inspection system and method. The compliance inspection system includes an interface for at least communicating an inspection assignment to an inspector, wherein the inspection assignment includes an inspection location indicting where an inspection is to occur and for receiving location data related to the inspector. The compliance inspection system also includes a processor executing instructions stored on a memory to analyze the received location data related to the inspector, verify the inspector is at the inspection location based on the analysis of the received location data, and receive inspection documentation related to the inspection from the inspector.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate, and the pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode, a first electrode, and a second electrode; the first transistor includes a first active region, the second transistor includes a second active region, the driving transistor includes a fourth active region, at least one of a doping concentration of the first active region and a doping concentration of the second active region is greater than a doping concentration of the fourth active region.

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region.

Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Abstract: A display panel comprises: a plurality of pixels formed on a surface of a substrate; one or more drive circuits formed on the surface to supply signals to the pixels lining up; and a plurality of conductor patterns formed on the surface, electrically separated from each other, and each partially configuring the drive circuit. The conductor patterns comprise: a first conductor pattern having a first element forming portion configuring a part of a first circuit element of the drive circuit; and a second conductor pattern having a second element forming portion configuring a part of a second circuit element of the drive circuit. A discharge portion to narrow an interval between the first and second conductor patterns so as to be partially narrower than an interval between the first and second element forming portions is provided to the first conductor pattern and/or the second conductor pattern.

Abstract: Provided herein are systems and methods for using multi-modal regression to predict customer intent to contact a merchant. Multi-modal data including numerical data and unstructured data are extracted from customer interactions with the merchant. Features of the numerical data and the unstructured data are separately extracted and classified using techniques specific to the data types. The features for each type are then separately used to predict probabilities of customer intent. A neural network is used to combine the predictions into a single set of estimates of customer intent. This set of estimates of customer intents is used to estimate a probability that the customer will contact the merchant. The customer is then contacted based on the estimate.

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.

Abstract: Provided are an image sensor and a manufacturing method thereof. In the image sensor, an insulating layer and a first silicon layer are sequentially on a silicon base. A first isolation structure is in the first silicon layer to define an active area (AA). A doped region is in a part of the first silicon layer in the AA and in a part of the silicon base thereunder. A second silicon layer is in a part of the first silicon layer in the AA and extends into the silicon base. An interconnection structure is on the first silicon layer and electrically connected with a transistor. A second isolation structure is in the silicon base under the first isolation structure and connected to the insulating layer. A passivation layer surrounds the silicon base and is connected to the doped region. A microlens is on the silicon base.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A display device includes a substrate having a display area and a non-display area surrounding the display area. A drain electrode is disposed in the display area and is positioned adjacent to the non-display area. A light emitting element is disposed in the display area and is connected to the drain electrode. The light emitting element is disposed farther from the non-display area than the drain electrode. A plurality of first dams is disposed in the display area and is positioned between the drain electrode and the light emitting element. Each of the plurality of first dams are spaced apart from each other.

Abstract: A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.

Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.