Patents Examined by Courtney A. Bowers
  • Patent number: 5493131
    Abstract: The rectifying element is comprised of two electrodes, an undoped diamond film, and a B-doped p-type diamond film. The diamond films are formed of highly-oriented diamond films, of which at least 80% of the surface area consists of (100) or (111) crystal planes, and the differences {.DELTA..alpha., .DELTA..beta., .DELTA..gamma.} of Euler angles {.alpha., .beta., .gamma.}, which represent the orientations of crystal planes, simultaneously satisfy .vertline..DELTA..alpha..vertline..ltoreq.5.degree., .vertline..DELTA..bet a..vertline..ltoreq.5.degree. and .vertline..DELTA..gamma..vertline..ltoreq.5.degree. between adjacent crystal planes. The diamond rectifying element thus constructed have an excellent electrical characteristics, and multiple of the elements can be produced on a large area at low cost. The diamond rectifying elements can be used for heat-resistant and high-power rectifying elements.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: February 20, 1996
    Assignee: Kobe Steel USA, Inc.
    Inventors: Koichi Miyata, Kimitsugu Saito, David L. Dreifus
  • Patent number: 5491348
    Abstract: A source electrode is formed on the first semiconducting diamond film and a drain electrode is formed on the second semiconducting diamond film. A highly resistant diamond film having a thickness of between 10 .ANG. and 1 mm and an electrical resistance of at least 10.sup.2 .OMEGA..cm or more is placed between the first and second semiconducting diamond films. A gate electrode is formed on the highly resistant diamond film. Thereby, a channel region is formed by these first and second semiconducting diamond films as well as the highly resistant diamond film. All or at least a part of said first and second semiconducting diamond films and the highly resistant diamond film are made of highly-oriented diamond films where either (100) or (111) crystal planes of diamond cover at least 80% of the film surface, and the differences {.DELTA..alpha., .DELTA..beta., .DELTA..gamma.} of Euler angles {.alpha., .beta., .gamma.} which represent the crystal plane orientation, satisfy .vertline..DELTA..alpha..vertline.<10.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: February 13, 1996
    Assignee: Kobe Steel USA, Inc.
    Inventors: Hisasi Koyamao, Koichi Miyata, Kimitsugu Saito, David L. Dreifus, Brian R. Stoner
  • Patent number: 5491359
    Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: February 13, 1996
    Assignee: INMOS Limited
    Inventors: Michael D. May, Jonathan Edwards, David L. Waller
  • Patent number: 5489788
    Abstract: In an insulated gate semiconductor device, a loss is suppressed and a short-circuit tolerance as well as a latch-up tolerance are improved. A saturation current I.sub.CE (sat) and a short-circuit tolerance tw are reduced without much influencing a collector-emitter saturation voltage V.sub.CE (sat) by setting a sheet resistance of an n-type emitter region 4 at a large value. When the sheet resistance is in the range between 40.OMEGA./.quadrature. and 150.OMEGA./.quadrature., 10 .mu.sec or more of the short-circuit tolerance, which is practically sufficient, is ensured while the collector-emitter saturation voltage V.sub.CE (sat) is suppressed to practically small 2.4 V or less. Both the collector-emitter saturation voltage V.sub.CE (sat) and the saturation current I.sub.CE (sat) are restrained small, thereby realizing an enhanced short-circuit tolerance.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: February 6, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Tomomatsu, Hiroshi Yamaguchi, Hiroyasu Hagino
  • Patent number: 5489785
    Abstract: A band-to-band resonant tunneling transistor including GaSb and InAs resonant tunneling layers separated by a thin barrier layer and a second InAs layer separated from the GaSb layer by another thin barrier layer. A terminal on the InAs resonant tunneling layer and a terminal on the second InAs layer. Leakage current reduction layers are positioned on the second InAs layer with a bias terminal positioned thereon. The InAs resonant tunneling layer has a plurality of quantized states which are misaligned with the ground state of the GaSb layer in a quiescent state, each of the quantized states of the InAs resonant tunneling layer are movable into alignment with the ground state of the GaSb layer to provide current flow through the transistor with the application of a specific potential to the terminal on the second InAs layer.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: February 6, 1996
    Assignee: Motorola
    Inventors: Saied N. Tehrani, Jun Shen, Herbert Goronkin, Xiaodong T. Zhu
  • Patent number: 5486709
    Abstract: In a breakover type surge protection device utilizing punch-through that comprises a second semiconductor region forming a first pn junction with a first semiconductor region, a third semiconductor region forming a second pn junction with the second semiconductor region and a fourth semiconductor region forming a third pn junction with the first semiconductor region at a place apart from the second semiconductor region, the second semiconductor region is constituted of a punch-through suppression region portion disposed to cover the corners of the third semiconductor region and a punch-through generation region portion disposed at a place where its thickness can be made uniform. Fabricating surge protection devices according to this configuration reduces variation among their breakover currents and hold currents and increases their surge absorption capacity.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: January 23, 1996
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry, Sankosha Corporation, Optotechno Co., Ltd.
    Inventors: Yutaka Hayashi, Masaaki Sato, Yoshiki Maeyashiki
  • Patent number: 5486705
    Abstract: A heterojunction FET comprises: a semi-insulation GaAs substrate; and a heterojunction structure, formed on the substrate, having: an active layer including: an undoped InGaAs layer including 10-254 of InAs composition; an undoped GaAs layer formed on the undoped InGaAs layer on the opposite side of the substrate; first and second AlGaAs layers doped with first and second dopants respectively, sandwiching the active layer, the second AlGaAs layer being provided between said active layer and the substrate; and source, gate, and drain electrodes on the heterojunction structure. A first density of the first dopant may be lower than a second density of the second dopant. The first and second dopant may be p or n type. The AlAs composition of the first AlGaAs layer may be lower than that of the second AlGaAs layer. First and second undoped AlGaAs layers sandwiched between the active layer and the first AlGaAs layer and sandwiched between the active layer and the second AlGaAs layer respectively may be provided.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: January 23, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Toshinobu Matsuno, Tadayosi Nakatuka, Hiroyuki Masato
  • Patent number: 5485032
    Abstract: A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum allow form a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the-germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: January 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Dominic J. Schepis, Kris V. Srikrishnan, Seshadri Subbanna, Manu J. Tejwani
  • Patent number: 5481119
    Abstract: A superconducting element includes a superconducting thin film bridge extending along the surface of a substrate, and a control electrode member for injecting quasi particles into a portion of an intersection region of the superconducting thin film bridge. The intersection region extends across the superconducting thin film bridge in a direction which is perpendicular to the current flow direction of the superconducting thin film bridge. A remaining portion of the intersection region, which is not injected with quasi particles by the control electrode member, operates as a weak-coupling bridge to thereby control the current flow within the superconducting thin film bridge.
    Type: Grant
    Filed: August 7, 1992
    Date of Patent: January 2, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetaka Higashino, Koichi Mizuno, Kentaro Setsune
  • Patent number: 5481131
    Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: January 2, 1996
    Assignee: Motorola, Inc.
    Inventors: Joseph Staudinger, Warren L. Seely, Howard W. Patterson
  • Patent number: 5477066
    Abstract: A heterojunction bipolar transistor includes a III-V compound semiconductor substrate having a surface; III-V compound semiconductor layers successively disposed on the surface including an InGaAs layer, an InP layer, and an InAlAs layer; and base electrodes in contact with the InGaAs layer wherein contact of the base electrodes with the InGaAs layer is coplanar with contact between the InP layer and the InGaAs layer.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: December 19, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masahiko Nakanishi
  • Patent number: 5471084
    Abstract: This invention relates to a magnetoresistive element used for a magnetic sensor, etc. A ferromagnetic magnetoresistive element thin film is formed so as to be electrically connected to and so as to overlap the upper end portion of an aluminum wiring metal on a substrate. Through using a vacuum heat treatment with a temperature between 350.degree. and 450.degree. C., a Ni--Al-based alloy is formed at the overlapping portion. Therefore, even when a surface protection film of silicon nitride is subsequently formed by plasma CVD on the substrate, the alloy prevents the nitriding of the upper end portion of the aluminum wiring metal. Accordingly, the surface can be protected from moisture by the silicon nitride film without increasing the contact resistance between the magnetoresistive element thin film and the wiring metal. Instead of the Ni--Al-based alloy, other conductive metals such as TiW, TiN, Ti, Zr, or the like may be used.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: November 28, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yasutoshi Suzuki, Kenichi Ao, Hirofumi Uenoyama, Hiroki Noguchi, Koji Eguchi, Ichiro Ito, Yoshimi Yoshino
  • Patent number: 5468973
    Abstract: A stacked Josephson junction device includes a pair of copper oxide superconductor layers and a non-superconductor layer formed between the pair of oxide superconductor layers. The copper oxide superconductor layers are composed of a compound copper oxide having the composition expressed by the general formula:LnBa.sub.2 Cu.sub.3 O.sub.v(where Ln is Y or rare earth element and 6<v.ltoreq.7).The non-superconductor layer is composed of a chemical compound having the composition expressed by the general formula:Bi.sub.2 Y.sub.x Sr.sub.y Cu.sub.z O.sub.w(where x, y, z and w indicate ratio of components0.ltoreq.x.ltoreq.2,1.ltoreq.y.ltoreq.3,1.ltoreq.z.ltoreq.3,6.ltoreq.w.ltoreq.13.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: November 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keizo Harada, Hideo Itozaki
  • Patent number: 5468972
    Abstract: A vacuum chamber is provided with an electron emission source on a first side wall, a collector on a second side wall opposite to the first side, and an insulated electrode on a bottom wall. Electrons emitted from the electron emission source move over the insulated electrode to be collected by the collector, so that the spatial position and the path of the electrons on the insulated electrode are controlled dependent on an electric potential generated by the insulated electrode.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: November 21, 1995
    Assignee: NEC Corporation
    Inventor: Keizo Yamada
  • Patent number: 5468989
    Abstract: There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: November 21, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Hirotaka Nishizawa, Seiichiro Azuma, Kazuaki Ootoshi, Masataka Miyama, Shuji Kawata, Osamu Kasahara, Sinichi Suzuki
  • Patent number: 5464993
    Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: November 7, 1995
    Assignee: Consorzio per la Ricerca sulla Microelectronica nel Mezzogiorno
    Inventors: Raffaele Zambrano, Sergio Palara
  • Patent number: 5464989
    Abstract: Each of the portions corresponding to the crossings of a plurality of first strip conductive layers serving as bit lines and a plurality of second strip conductive layers serving as word lines crossing the conductive layers at right angles is used as one memory cell. An oxide film is provided between the first strip conductive layers and the second strip conductive layers. The thickness of this oxide film is set in each memory cell according to stored data. Also a multi-value memory can be realized, since the amount of stored data in each memory cell is an arbitrary amount of 1 bit or more by making the stored data of a plurality of types of memory cells having different thicknesses in the tunnel oxide film 15 correspond to a plurality of different data. The size of each memory cell can be reduced since the occupying area of each memory cell on the semiconductor substrate is dependent on the width of the first strip conductive layer and the second strip conductive layer.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: November 7, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Mori, Osamu Ueda, Masayuki Yamashita
  • Patent number: 5461248
    Abstract: A trench capacitor memory cell having a semiconductor substrate, an active region having a transistor on a portion of the semiconductor substrate, a field region formed by removing portion of the semiconductor substrate except for portions of the active region to a certain depth below the surface of the semiconductor substrate, a capacitor trench region formed in contact with a part of the active region and within the field region, and a polysilicon plug formed within the field region except for the trench region, and insulated by being surrounded by an insulating layer.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: October 24, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Young-Kwon Jun
  • Patent number: 5457331
    Abstract: A dual-band HgCdTe radiation detector (10) includes a four layer n-p.sup.+ -p-n.sup.+ structure, grown by LPE, upon a substrate (12). The four layers are, from a bottom layer next to the substrate to the surface: (a) a MWIR radiation responsive n-type absorbing layer (14); (b) a p.sup.+ cap layer (16); (c) a LWIR radiation responsive p-type layer (18); and (d) an n+ top layer (20). The n.sup.+ top layer has a compositional profile that is similar to the p-type cap layer. Operation of this structure involves biasing the top layer positive with respect to the bottom layer, which results in the collection of LWIR-generated electrons in the p-type layer. Biasing the top layer negative with respect to the bottom layer results in MWIR-generated holes being collected by the bottom n-p+ junction.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: October 10, 1995
    Assignee: Santa Barbara Research Center
    Inventors: Kenneth Kosai, George R. Chapman
  • Patent number: 5455185
    Abstract: In an epitaxial layer (3) deposited on a substrate (1), emitter (14), base (6) and collector (15) are disposed in a vertical sequence in such a way that the emitter (14) adjoins the surface of the epitaxial layer. Emitter (14) and base (6) are laterally bounded by an insulating zone (4, 8). The base (6) has, at the edge adjacent to the insulating zone, a base edge region (61) which is more heavily doped than the rest of the base (6). The base edge region (61) is produced, in particular, by outdiffusion from the borosilicate glass spacers (8) disposed on top of it.
    Type: Grant
    Filed: August 3, 1993
    Date of Patent: October 3, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventor: Helmut Klose