Abstract: A vertical ferroelectric capacitor structure and the method of fabricating the same. An insulating layer is formed on a semiconductor substrate. A lower opening and an upper opening with the depth larger than the width are defined and formed in the insulating layer. A conductive material is filled into the openings to form two vertical and parallel plate electrodes to serve as lower electrode and upper electrode. A portion of the insulating layer between the lower and upper electrodes are then removed to form a gap between the lower and upper electrodes. A ferroelectric material is filled into the gap to form a ferroelectric capacitor with vertical structure.

Abstract: A semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate includes a protective layer formed on the surface of the interlevel insulating film that has a lower polishing rate than that of the interconnection material in chemical mechanical polishing. A method of manufacturing this semiconductor device is also disclosed.

Abstract: Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: A method of decreasing the growth rate of silicon dioxide films on a silicon nitride pad on a silicon wafer wherein the decrease in growth rate of the silicon dioxide results in a self-planarized film on the wafer is provided. Also provided is a method of pretreating said silicon wafer wherein said wafer is contacted with a chemical, such as hydrogen peroxide, isopropyl alcohol or acetone and air-dried prior to silicon dioxide deposition. Additionally, selective oxidation sub-atmospheric chemical vapor deposition (SELOX SACVD) uses an ozone-activated tetraethylorthosilicate process to deposit said silicon dioxide on said wafer.

Abstract: A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.

Abstract: A process flow for forming a sacrificial collar (132) within a deep trench (113) of a semiconductor memory cell. A nitride liner layer (120) is deposited over a substrate (111). A thin polysilicon layer (122) is deposited over the nitride liner layer (120), and an oxide layer (124) is formed. A resist (116) is deposited within the trenches (113) and etched back. The top portion of the oxide layer (124) is removed, and the resist (116) is removed from the trenches (113). The wafer (100) is exposed to a nitridation process to form a nitride layer (128) over exposed portions of the polysilicon layer (122). The oxide layer (124) and polysilicon layer (124) are removed from the bottom of the trenches. (113). The nitride liner layer (120) is removed from the bottom of the trenches (113). The polysilicon layer (122) is removed from the top of the trenches (113) to leave a sacrificial collar (132) in the top of the trenches 113 formed by nitride liner layer (120).

Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

Abstract: A method of dicing a wafer from the back side surface thereof comprises the steps of: providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips; forming a through structure corresponding to the scribe lines on the active surface of the wafer; and dicing the wafer from the back side surface of the wafer according to the through structure as positioning reference marks.

Abstract: A method of rubbing for a liquid crystal display device includes the steps of rubbing an orientation film on a substrate using a first rubbing fabric, detecting defects of the orientation film, and repeating the step of rubbing the orientation using a second rubbing fabric when the defects are detected.

Abstract: MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g.

Abstract: A method of forming metal thin film of a memory device includes the steps of forming a metal layer on a semiconductor substrate, forming uniform grains on a surface of the metal layer, and forming a dielectric layer on the metal layer.

Abstract: Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material.

Abstract: A method is provided herein for trim etching a resist line in a plasma etch apparatus. The method provides a reduced rate of vertical direction etching of the resist, and an increased rate of horizontal direction etching of the resist, by applying a lower biasing power to the plasma etch apparatus that is conventionally used. The resulting resist has an increased height in relation to its width which adds to the structural integrity of the resist line and significantly reduces problems of discontinuity in the resist line.

Abstract: Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI) technology enhanced by selectively implanting the bottom surface of the trench with dopant diffusion inhibiting ions prior to filling the trench with a dielectric material and formation of opposite conductivity type well regions on either side of the trench. The inventive methodology effectively reduces or substantially eliminates deleterious counterdoping of the subsequently formed well regions resulting from thermally-induced lateral inter-diffusion of p-type and/or n-type dopant impurities used for forming the well regions.

Abstract: An intermediary dielectric layer is disposed between two dielectric layers thereby eliminating a flow stabilization step that may produce unwanted deposition that leads to peeling. A wafer is provided having an HDP layer. An undoped silicon glass layer is deposited on top of the HDP layer to improve adherence of a subsequently deposited PSG layer.

Abstract: The present invention provides a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of: forming the first planar substrate, attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer; attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer; partly curing the polymer adhesive layer, disconnecting the release layer from the first substrate to separate the first substrate from the camer, followed by coing the polymer adhesive layer.

Abstract: A semiconductor device and a method of making a semiconductor device. A damascene metal layer (16) is formed in an insulating dielectric layer (12), which is in direct electrical communication with a substrate (10). A layer of a passive element, such as first capacitor electrode layer (20) is disposed on metal layer (16) and preferably is offset relative to metal layer (16) to allow a direct electrical interconnect through a via (36) to metal layer (16). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor (28) and optionally a second resistor (32). In yet another embodiment, metal layer (16) is a damascene copper layer.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack comprising one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.