Abstract: A method of manufacturing metallic interconnects. A substrate has a copper line formed therein. An inter-metal dielectric layer is formed over the substrate and the copper line. A patterned photoresist layer is formed over the inter-metal dielectric layer. The inter-metal dielectric layer is etched to form a trench and a contact opening that exposes a portion of the copper line, wherein the contact opening is under the trench. At a low temperature and using a plasma derived from a gaseous mixture N2H2 (H2:4%)/O2, the photoresist layer is removed. Any copper oxide layer formed on the copper line in the process of removing photoresist material is reduced back to copper using gaseous N2H2 (H2:4%). A barrier layer conformal to the trench and the contact opening profile is formed. Copper is deposited to form a conformal first copper layer over the trench and the contact opening.

Abstract: A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a substrate; an active region in the substrate, the active region being formed in a direction; gate electrodes of the first and second access transistors crossing the active region, the gate electrodes of the first and second access transistors are parallel with each other; gate electrodes of the first and second drive transistors crossing the active region, the gate electrodes of the first and second drive transistors are parallel with each other; and first and second load devices on the gate electrodes of the first and second access transistors, the first and second load devices are parallel with each other.

Abstract: A selected passivating layer is purposely formed on an exposed surface of a Cu and/or Cu alloy interconnect member, thereby avoiding the adverse consequences stemming from formation of a thick copper oxide layer thereon. The passivating layer is formed by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) with a copper corrosion-inhibiting chemical; or (b) by electroless plating a metal layer on the surface of the Cu or Cu alloy layer; or (c) depositing a metallic compound on the surface of the Cu or Cu alloy layer by CVD. The passivating layer can then be removed. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in an ILD, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the passivating, layer thereon, and depositing a silicon nitride diffusion barrier layer thereon.

Abstract: A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device (10) having at least one metal layer (28) completed. Then, a planarizing dielectric layer (30) is added to the semiconductor device (10). The semiconductor device (10) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device (10).

Abstract: In a method for fabricating a thin film of polymer, particularly a semiconducting thin film of polymer with an improved structural order, wherein the thin film is formed by deposition of a polymer material onto a solid substrate material from a polymer solution formed by means of a solvent, the polymer solution is provided in a closed container such that a free volume is left in the container above the polymer solution and the substrate material immersed in the solution, whereupon the substrate material with a thin film deposited thereon is withdrawn from the polymer solution with a withdrawal speed being selected dependent on the concentration of the polymer solution, until the substrate material is located in the free volume a certain distance above the polymer solution. The substrate material is kept in vertical position in the free volume while the solvent evaporates, whereupon the substrate material with the thin film is removed from the container for further drying in a vacuum oven.

Abstract: A device isolation structure and a method thereof including a semiconductor substrate wherein a field isolation region including a plurality of dummy active regions and an active region are defined, a plurality of trenches formed among the regions, a filling layer filled in the plurality of trenches, a gate insulation layer formed on the semiconductor substrate having the filling layer, and a second conduction layer formed on the gate insulation layer, is capable of preventing a dishing from being generated in etching by forming the plurality of dummy active regions in the field isolation region and basically preventing the wide trenches from being formed, minimizing a parasitic capacitance generated in the dummy active-gate insulation layer-gate insulation layer in the field isolation region, and simplifying an isolation process by using the dummy active pattern.

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.

Abstract: A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditions as the MOS transistor forming step. Only a single mask needs to be modified for the programming, thus reducing cost and complexity of manufacturing the device.

Abstract: A semiconductor chip interposer increases fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE. The semiconductor chip interposer includes a thin metal plate having a plurality of through holes, the thin metal plate having a TCE intermediate the relatively high TCE and the relatively low TCE. An insulation coating on the thin metal plate is also included on walls of the through holes. An electrical conductive material fills each of the insulated through holes for electrical interconnection between the first component and the second component.

Abstract: A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2 O3 can be used.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A method of fabricating a thin film transistor includes the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the metal layer; etching the metal layer and the insulating layer by using the photoresist pattern as a mask, and respectively forming a gate electrode and a gate insulating layer to expose a part of the active layer; forming an amorphous silicon layer on the resultant whole surface substrate; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer and a source/drain electrode; and carrying out a lift-off process to remove the photoresist pattern, and exposing the surface on the gate electrode.

Abstract: A nonvolatile semiconductor memory cell array is shown which is composed of a plurality of unit cell-arrays arranged in a repeating pattern. Each of the unit cell-arrays includes a first plurality of cell transistors having control gates coupled in common to a first word line and a second plurality of cell transistors having control gates coupled in common to a second word line. The two word lines are arranged in parallel to one another and perpendicular to a bit line. The bit line is connected in common with drains of both the first and second plurality of cell transistors through a bit line contact. A pair of source lines is arranged along each side of the bit line and parallel to the bit line. Each source line is coupled to one transistor from each of the first and second pluralities of cell transistors through a source line contact.

Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench.

Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Abstract: A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72). The method involves forming steps (104) in the sidewalls of the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).