Abstract: A method of forming a self-aligned contact on a semiconductor includes forming a layer of a dielectric material over a semiconductor, providing a photoresist layer over the dielectric layer and then exposing the photoresist layer with a desired pattern and developing an opening in the photoresist layer. The dielectric material exposed through the photoresist layer opening is then removed to form a contact opening extending through the dielectric material to the semiconductor. The photoresist layer is then eroded so as to enlarge the size of the opening in the photoresist layer, whereby the dielectric material adjacent the contact opening is exposed through the enlarged opening of the photoresist layer. A barrier metal is then deposited in the enlarged opening of the photoresist layer and in the contact opening of the dielectric material, whereby the barrier metal overlies the exposed portion of the dielectric material. A conductive metal is then deposited atop the barrier metal.

Abstract: In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.

Abstract: A process for fabricating a fin type, cylindrical shaped, DRAM capacitor structure, with increased surface area, has been developed. The process features forming a non-continuous layer of discrete regions of silicon, on the surface of a capacitor opening, in a composite insulator layer. The discrete regions of silicon are then used as an etch mask to allow an isotropic etching procedure to create horizontal channels in the sides of the portions of the composite insulator layer exposed in the capacitor opening, creating a capacitor opening comprised with horizontal channnels. An amorphous silicon layer is then deposited and patterned to form a fin type, storage node structure, comprised of amorphous silicon on discrete regions of silicon, in the capacitor opening. Formation of a capacitor dielectric layer, and an overlying top electrode structure, complete the formation of a fin type, cylindrical shaped, DRAM capacitor structure.

Abstract: A substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer. And then dry etching is carried out by means of the first photoresist layer as the mask to form a via hole. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is defined and formed on the second dielectric layer. Dry etching is proceed, and etching stop layer is as a etching terminal point to remove exposed partial surface of the second dielectric layer so as to form a trench having larger horizontal size than the via hole. Subsequently, the second photoresist layer is removed to form the opening of the damascene.

Abstract: A method of formation of a damascene FSG film with good adhesion to silicon nitride in an HDP-CVD system. Silane (SiH4), silicon tetrafluoride (SiF4), oxygen (O2) and argon (Ar) are used as the reactant gases. SiH4, SiF4, and O2 react to form the FSG. Ar is introduced to promote gas dissociation. All four gases are used for depositing most of the FSG film. SiH4 is not used during deposition of the interfacial part of the FSG film. The interfacial part of the FSG film refers either to the topmost portion, if silicon nitride is to be deposited on top of the FSG or the bottom portion if the FSG is to be deposited on top of silicon nitride. Using SiH4 with the SiF4 tends to mitigate the destructive effects of SiF4 throughout most of the deposition. By removing the SiH4 from the deposition of the interfacial part of the FSG film less hydrogen is incorporated into the film in the interfacial region and adhesion to overlying or underlying silicon nitride is improved.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: A silicon film is formed on a semiconductor substrate, and a silicon oxide film and a polycrystalline silicon film are formed thereon. Patterning is performed for the polycrystalline silicon film to form a capacitive upper electrode. Then, patterning is performed for the silicon oxide film to form a capacitive dielectric film below the capacitive upper electrode, the capacitive dielectric film having a shape larger than that of the capacitive upper electrode. Subsequently, an anti-reflection coating film (silicon nitride film which is silicon-rich) is formed on a full surface. Then, patterning is performed for the silicon film by means of photolithography to form a capacitive lower electrode and a gate electrode of a transistor.

Abstract: In one aspect, a method is disclosed. The method comprises introducing a plurality of integrated circuits on a substrate, each integrated circuit separated from another by a scribe line area and introducing a masking material over a portion of the scribe line area. Following the introduction of the masking material, the method further includes introducing a material comprising a colorant over a portion of each of the plurality of integrated circuits and singulating the plurality of integrated circuits.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches.

Abstract: Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.

Abstract: A process for forming metal structures, encapsulated in silicon rich oxide, (SRO), shapes and layers, needed to protect the metal structures from the corrosive effects of fluorine radicals, present in low k, fluorinated silica glass, (FSG), which in turn is formed in the spaces between metal structures, has been developed. The process features initial formation of the metal structures, capped with an overlying SRO shape. This is followed by the formation of SRO spacers on the sides of the SRO capped, metal structures. Another thin, conformal SRO layer is then deposited to insure encapsulation of the metal structures, however still leaving adequate space between the SRO encapsulated metal structures for the low k FSG layer, needed to limit capacitance and improve device performance.

Abstract: A softened and compliant fillet portion of a cured polymeric underfill in a flip-chip arrangement reduces occurences of fillet crackings caused by thermal stresses. The softening of the fillet is achieved by chemically breaking cross-links in the cured polymeric underfill material using a chemical solvent. In another embodiment, the softening of the fillet is achieved by applying heat using a controllable beam of thermal energy to break up the cross-links to thereby soften the fillet.

Abstract: A method of patterning a metal layer includes masking a first portion of a metal layer while leaving a second portion of the metal layer unmasked over a substrate. With the masking in place, the second portion is reacted with silicon to form a metal silicide from the metal layer. The metal silicide is removed from the substrate while substantially leaving the first portion on the substrate. The masking is removed from the substrate. A method of patterning a metal layer includes depositing and patterning a silicon comprising layer over a substrate. A metal layer is formed over the patterned silicon comprising layer, and includes a portion extending to elevationally inward of the metal layer. Metal of the metal layer is reacted with silicon of the silicon layer to form a metal silicide and leave at least some of the portion unreacted. The metal silicide is removed from the substrate while substantially leaving the unreacted portion of the metal layer on the substrate.

Abstract: A low temperature process is described for forming a low dielectric constant (k) fluorine and carbon-containing silicon oxide dielectric material for integrated circuit structures. A reactor has a semiconductor substrate mounted on a substrate support which is maintained at a low temperature not exceeding about 25° C., preferably not exceeding about 10° C., and most preferably not exceeding about 0° C. A low k fluorine and carbon-containing silicon oxide dielectric material is formed on the surface of the substrate by reacting together a vaporous source of a mild oxidizing agent, such as a vaporized hydrogen peroxide, and a vaporous substituted silane having the formula (CFmHn)—Si—(R)xHy wherein m is 1-3; n is 3-m; R is an alkyl selected from the group consisting of ethyl (—C2H5), methyl (—CH3), and mixtures thereof; x is 1-3; and y is 3-x.

Abstract: A method of manufacturing a compound semiconductor is provided which can produce a mixed crystal layer with high nitrogen content without lowering the crystallinity when a III-V compound semiconductor layer including nitrogen and at least another V group element is grown by molecular beam epitaxy.

Abstract: Extremely high dopant concentrations are uniformly introduced into a semiconductor material by laser annealing aided by an anti-reflective coating (ARC). A spin-on-glass (SOG) film containing dopant is formed on top of the semiconductor material. An ARC is then formed over the doped SOG layer. Application of radiation from an excimer laser to the ARC heats and melts the doped SOG film and the underlying semiconductor material. During this melting process, dopant from the SOG film diffuses uniformly within the semiconductor material. Upon removal of the laser radiation, the semiconductor material cools and crystallizes, evenly incorporating the diffused dopant within its lattice structure. The ARC suppresses reflection of the laser by the doped material, promoting efficient transfer of energy from the laser to heat and melt the underlying doped layer and semiconductor material.

Abstract: There is disclosed a method of manufacturing a capacitor in a semiconductor device capable of effectively removing the organic impurity of a Ta2O5 film by performing an in-situ plasma process using the mixture gas of nitrogen and oxygen during the process of forming the Ta2O5 film as the dielectric film of the capacitor. Thus, it can reduce the impurity of the Ta2O5 film to increase the supply of oxygen, and thus can improve the dielectric and leak current characteristic of the Ta2O5 film. Further, it can prohibit oxidization of the underlying electrode, thus reducing the thickness of the equivalent oxide film of the capacitor as possible and sufficiently securing the capacitance of the capacitor.

Abstract: A transistor having a gate insulation layer whose peripheral portion has an increased thickness and a method of fabricating these transistor devices is disclosed. The peripheral portions with increased thickness of the gate insulation layer significantly reduce the injection of charge carriers into the gate insulation layer. Accordingly, the transistors described in the present application exhibit an improved long-time reliability. In addition, the lateral penetration of ions beneath the gate insulation layer for forming the lightly-doped drain and/or the lightly doped source is increased since the implantation may be performed at a tilt angle with respect to the perpendicular direction which is the conventionally used direction of the implantation step.