Abstract: The present invention provides an improved fluorinated polymer encapsulant for protectively coating electronic devices in an electronic device module. Also provided is a method for applying and reworkably removing the same to and from the electronic device module. In one embodiment, a coating of a fluorinated polymer solution is applied to at least a portion of an electronic device module. The module is then baked to operably fix to it the fluorinated polymer coating.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: A method for fabricating an embedded semiconductor device in which a logic device and a memory device are integrated into one semiconductor substrate is disclosed, which includes the steps of forming a device isolation region and active region on a semiconductor substrate having a first region and a second region, forming a gate insulation film on a predetermined portion of an upper surface of the active region of the first region and second region, forming a first conductive film pattern and a protection film pattern on the gate insulation film, forming a first side wall spacer on the lateral surfaces of the first conductive film pattern and the protection film pattern, forming source/drain by implanting a dopant into the surface of the semiconductor substrate at both sides of the first side wall spacer, forming a second side wall spacer on an outer surface of the first side wall spacer, removing the protection film pattern, and forming a second conductive film pattern on the upper surfaces of the first cond

Abstract: A method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide layer is developed based upon the physics of deposition and sputtering and based upon the minimum geometry of features in the semiconductor device. First the geometric parameters of the metal features are determined. Then, based upon the most aggressive aspect ratio between metal lines, the deposition rate to sputter rate ratio is calculated. The film thickness for optimum global planarity is determined based on the calculated ratio. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.

Abstract: The invention also relates to an a method of fabrication of an integrated circuit, the method includes altering a portion of a surface layer of a material to be polished and polishing the surface layer in a chemical mechanical polishing process. Preferably, the step of altering of the present invention includes adding an impurity to the material such as a dopant by heavy ion implantation at a concentration level of about 1×1010 ions/cm2 to about 1×1018 ions/cm2.

Abstract: A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned.

Abstract: This invention provides a process for making an insulation layer for use in microelectronic devices, whereby capacitive coupling and propagation delay in the microelectronic devices are reduced. This invention can include the formation of a stable solution of nanometer-scale particles consisting of an inorganic core 10 that is decorated with a known number of fullerene molecules 20, and including a soluble component that can act to bind the particles together into an integral structure. This solution can be applied to a microelectronic substrate, and dried to form a continuous, porous layer. Porous layers formed by the process of this invention possess a very low dielectric constant, and can be produced using equipment and techniques common and available to those skilled in the art of microelectronic fabrication.

Abstract: A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.

Abstract: A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the stan

Abstract: In a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predetermined depth from the predetermined surface of the semiconductor substrate. Furthermore, a second dopant is implanted into the preamorphization junction with a dopant profile along a depth of the semiconductor substrate from the predetermined surface of the semiconductor substrate. A peak of the dopant profile is located at a fraction of the first predetermined depth of the preamorphization junction. A silicidation RTA (Rapid Thermal Anneal) is performed to form silicide on the semiconductor substrate. The silicidation RTA (Rapid Thermal Anneal) recrystallizes the preamorphization junction from the first predetermined depth of the preamorphization junction up to an unrecrystallized depth of the preamorphization junction.

Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Abstract: A lead member includes a plurality of conductors arranged in parallel and an insulating film fixing the conductors at a predetermined pitch. Each conductor includes a first end portion, a second end portion, and a flat portion extending between the first and second end portions. The flat portion is located on a plane different from a plane on which the first end portion and the second end portion lie. The flat portion may be formed by bending the lead member along a bent line such that the bent line is kept straight. Preferably, each conductor includes a narrow portion and a wide portion, wherein a width of each conductor along the bent line is greater than half of the pitch between adjacent conductors.

Abstract: A method of forming a crystalline silicon well over a perovskite barrier layer, preferably for use in formation of a resonant tunneling diode. A silicon substrate (1) is provided of predetermined crystallographic orientation. A layer of crystallographic perovskite material (5) is formed over the silicon substrate and substantially matched to the lattice constant of the silicon substrate. A layer of crystallographic silicon (7) is formed over the perovskite layer substantially matched to the lattice constant of the perovskite layer. The perovskite layer is formed by the steps of placing the silicon substrate in a chamber and then evaporating a layer of barium strontium oxide (3) thereon with a thickness of from about three to about six Angstroms and then evaporating a layer of calcium strontium titanate (5) thereon having a thickness of from about six to about 25 Angstroms thereon in the case of a tunneling diode.

Abstract: Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.

Abstract: A method of fabricating a barrier layer includes a clamped metal layer formed on a substrate. After the formation of the clamped metal layer, a rapid thermal process is performed. A clampless metal nitride layer is then formed on the clamped metal layer.

Abstract: An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide (“FOX”), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside own NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e.

Abstract: A method for fabricating a transistor having a variable threshold voltage is disclosed. Energy levels of a transistor can be represented by a valance band, a conduction band, and a Fermi level. In order to fabricate a transistor with a variable threshold voltage, a region of the transistor is initially doped with a first dopant having a first energy level below the Fermi level. The region of the transistor is subsequently doped with a second dopant having a second energy level above the Fermi level. Alternatively, the region of the transistor can be initially doped with a first dopant having a first energy level above the Fermi level, and then the region of the transistor can be subsequently doped with a second dopant having a second energy level below the Fermi level.

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.

Abstract: A method for making conductive plugs in a semiconductor wafer. In involves the steps of: (a) forming at least one through hole in a dielectric layer, which is formed above a conductive substrate; (b) subjecting the wafer to a NH4OH/H2O2 wet washing process and HCl/H2O2 wet washing process; (c) drying the wafer; (d) subjecting the wafer to a dilute hydrogen fluoride or buffered hydrogen fluoride wet washing process to remove the native oxide layer that maybe formed on the conductive substrate; (e) drying the wafer again; and (i) filling the at least one through hole with a conductive material to form at least one conductive channel. The wet washing station is modified such that the wet washing processes and the drying process are performed in the same station and without removing the wafer from the washing station during the wet washing and drying process.

Abstract: A method for planarizing a damascence structure, comprises using two polishing procedure to remove the redundant metal layer. The method comprises depositing a dielectric layer over a wafer. A photolithography and etching procedure is then performed to form trenchs on the dielectric layer. Then, a metal layer is deposited over the dielectric layer and fills the trenchs. Thereafter, a electrical polishing and chemical mechanical polishing method is performed to remove metal layer until the dielectric layer is exposed. The invention is capable of reducing the dishing and erosion effects occurred on the metal layer.