Patents Examined by Craig Thompson
  • Method using planarizing gate material to improve gate critical dimension in semiconductor devices
    Patent number: 6787439
    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Cyrus E. Tabery, Haihong Wang, Bin Yu
  • Post-planarization clean-up
    Patent number: 6787473
    Abstract: Methods for removing residuals from the surface of an integrated circuit device. Such methods find particular application in the fabrication of a dual damascene structure following removal of excess portions of a silver-containing metal layer from a device surface. The methods facilitate removal of particulate residuals as well as unremoved portions of the metal layer in a single cleaning process. The cleaning solutions for use with the methods are dilute aqueous solutions containing hydrogen peroxide and at least one acidic component and are substantially free of particulate material. Acidic components include carboxylic acids and their salts.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Michael T. Andreas
  • Determining method of thermal processing condition
    Patent number: 6787377
    Abstract: The invention is a method of determining a set temperature profile for a method of controlling respective substrate temperatures of a plurality of groups in accordance with respective corresponding set temperature profiles, in a method of heat processing a plurality of substrates that are classified into the plurality of groups.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: September 7, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Wenling Wang, Koichi Sakamoto, Fujio Suzuki, Moyuru Yasuhara
  • Integrated circuit device characterization
    Patent number: 6789236
    Abstract: One or more electrical characteristics of an integrated circuit device are measured at one or more relatively lower frequencies. One or more parameters of the integrated circuit device are measured at one or more frequencies higher than the one or more relatively lower frequencies. One or more parameters of the integrated circuit device are calculated based on the measured one or more electrical characteristics. The integrated circuit device is characterized based on the calculated one or more parameters and the measured one or more parameters.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: September 7, 2004
    Assignee: Intel Corporation
    Inventor: Donald S. Gardner
  • Semiconductor device
    Patent number: 6784497
    Abstract: A semiconductor device according to the invention of the present application comprises a first semiconductor layer, a first insulating layer formed over the first semiconductor layer, a second semiconductor layer formed over the insulating layer, a protective element formed over the second semiconductor layer, an electrode pad, and a plurality of series-connected through holes for connecting the electrode pad and the protective element. Thus, a surge voltage applied across a diffused resistor can be lightened and hence an oxide film placed below the diffused resistor can be prevented from destruction.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: August 31, 2004
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Masafumi Nagaya
  • Method of making semiconductor-on-insulator device with thermoelectric cooler
    Patent number: 6784073
    Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: August 31, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Philip A. Fisher
  • Semiconductor component having conductors with wire bondable metalization layers
    Patent number: 6784544
    Abstract: A semiconductor component includes a semiconductor die, a low k polymer layer on the die and redistribution conductors on the polymer layer. The component also includes bonding pads on the conductors with a metal stack construction that includes a conductive layer, a barrier/adhesion layer and a non-oxidizing layer. The bonding pads facilitate wire bonding to the component and the formation of reliable wire bonds on the component. A method for fabricating the component includes the steps of forming the conductors and bonding pads using electroless deposition. The component can be used to fabricate electronic assemblies such as modules, packages and printed circuit boards.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Method of manufacturing silicon
    Patent number: 6784079
    Abstract: A production method of silicon which comprises the steps of bringing a silane into contact with a surface of a substrate so as to cause silicon to be deposited while the surface of the substrate is heated to and kept at a temperature lower than the melting point of the silicon, and raising the temperature of the surface of the substrate so as to cause a portion or all of the deposited silicon to melt and drop from the surface of the substrate and be recovered.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: August 31, 2004
    Assignee: Tokuyama Corporation
    Inventors: Satoru Wakamatsu, Hiroyuki Oda
  • PATTERN FORMING METHOD, METHOD OF MAKING MICRODEVICE, METHOD OF MAKING THIN-FILM MAGNETIC HEAD, METHOD OF MAKING MAGNETIC HEAD SLIDER, METHOD OF MAKING MAGNETIC HEAD APPARATUS, AND METHOD OF MAKING MAGNETIC RECORDING AND REPRODUCING APPARATUS
    Patent number: 6780738
    Abstract: All the electrode films corresponding to respective metal materials are laminated on a substrate beforehand, a first electrode film located farthest from the substrate is formed with a first metal pattern suitable for the first electrode film, and then the first electrode film is etched away so as to expose a second electrode film located lower than the first electrode film. Therefore, the second electrode film suitable for a metal material of a second metal pattern can selectively be plated, whereby the second metal pattern can be formed while optimizing the combination of its metal material and electrode film. Also, the second electrode film for the later step does not attach to the previously formed first metal pattern.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: August 24, 2004
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Stencil mask and method of producing the same, semiconductor device produced using the stencil mask and method of producing the semiconductor device
    Patent number: 6780659
    Abstract: A stencil mask is disclosed which can be produced by performing pattern correction in a practically applicable comparatively short period of time. When stencil mask pattern data are corrected by a stress analysis, displacement amounts are calculated for those of stencil hole patterns which have a size equal to or greater than a predetermined size. As a result, stencil mask pattern data having corrected patterns are obtained in a comparatively short period of time which can be applied industrially. By producing a stencil mask based on the patterns, a stencil mask in which a desired pattern is formed is obtained.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: August 24, 2004
    Assignee: Sony Corporation
    Inventor: Isao Ashida
  • Method of controlling the resistivity of Gallium Nitride
    Patent number: 6777315
    Abstract: A method of controlling the resistivity of gallium nitride is disclosed. The method incorporates an MBE system and utilizes solid source gallium, gaseous source nitrogen and solid source Buckminster Fullerene C60 as a carbon dopant for the GaN film. A desired, predetermined GaN film resistivity can be created during the growth process by selecting the temperature of the effusion cell containing the C60 within a predetermined range so as to impart the desired resistivity in the GaN film.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: August 17, 2004
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Joseph E. Van Nostrand
  • Edge and bevel cleaning process and system
    Patent number: 6777338
    Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: August 17, 2004
    Assignee: Nutool, Inc.
    Inventors: Jalal Ashjaee, Rimma Volodarsky, Cyprian E. Uzoh, Bulent M. Basol, Homayoun Talieh
  • Apparatus and methods for determining floating body effects in SOI devices
    Patent number: 6777708
    Abstract: Methods and systems are described for determining floating body delay effects in an SOI wafer, wherein test apparatus is provided in a wafer comprising a plurality of floating body devices fabricated in series in the wafer, and a pulse generation circuit providing a pulse output corresponding to a delay time associated with the floating body chain according to an input pulse edge and a propagated pulse edge from the floating body devices.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 17, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hung-Jen Lin, W. Eugene Hill
  • Fill pattern generation for spin-on-glass and related self-planarization deposition
    Patent number: 6777813
    Abstract: A fill pattern for a semiconductor device such as a memory cell. The memory cell includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: August 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Werner Juengling, Philip J. Ireland
  • Apparatus and methods for characterizing floating body effects in SOI devices
    Patent number: 6774395
    Abstract: Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hung-Jen Lin, W Eugene Hill, Mario M. Pelella, Chern-Jann Lee, Srikanth Sundararajan, Siu May Ho
  • Method for fabricating shallow trench isolation between deep trench capacitors
    Patent number: 6774008
    Abstract: The present invention studs oxide dielectric into trench capacitor top recesses after the formation of the trench capacitor structures. A thin (500 Å) cap buffer nitride is then deposited over the substrate. The studded dielectric and the collar oxide protect the trench capacitors during the subsequent selective dry etching, thereby forming isolation trenches having an approximately T-shaped cross section between the trench capacitors within the memory array area of the semiconductor chip.
    Type: Grant
    Filed: September 7, 2003
    Date of Patent: August 10, 2004
    Assignee: United Microeletronics Corp
    Inventors: Yi-Nan Su, Nathan Sun
  • Storage capacitor of planar display and process for fabricating same
    Patent number: 6773467
    Abstract: A storage capacitor of a planar display is disclosed. The storage capacitor includes a substrate, a lower electrode, an insulator layer, and an upper electrode in space order. The lower electrode is made of a semiconductor material such as polysilicon. The upper electrode is made of metal or polysilicon. For the metallic upper electrode, the upper electrode is patterned to have a comb, fishbone or net shape in order to allow dopants penetrating therethrough to reach the lower electrode, thereby increasing the conductivity of the lower electrode. A process for fabricating such storage capacitor is also disclosed. For the case that both the upper and lower electrodes are made of polysilicon, two doping procedures of different doping intensities are performed to provide dopants for the upper and lower electrodes, respectively.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 10, 2004
    Assignee: Toppoly Optoelectronics Corp.
    Inventor: An Shih
  • Method of manufacturing a top-emitting OLED display device with desiccant structures
    Patent number: 6770502
    Abstract: This invention provides a top-emitting OLED display device that includes a substrate; an array of OLED elements disposed on one side of the substrate; and a desiccant material provided in a patterned arrangement over the array of OLED elements on the same side of the substrate such that the desiccant material does not interfere with the light emitted by the OLED elements.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: August 3, 2004
    Assignee: Eastman Kodak Company
    Inventors: Ronald S. Cok, Michael L. Boroson, Terrence R. O'Toole
  • Method for manufacturing a semiconductor device
    Patent number: 6770518
    Abstract: The crystallization method by laser light irradiation forms a multiplicity of convexes (ridges) in the surface of an obtained crystalline semiconductor film, deteriorating film quality. Therefore, it is a problem to provide a method for forming a ridge-reduced semiconductor film and a semiconductor device using such a semiconductor film. The present invention is characterized by heating a semiconductor film due to a heat processing method (RTA method: Rapid Thermal Anneal method) to irradiate light emitted from a lamp light source after crystallizing the semiconductor film by laser light, thereby reducing the ridge.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: August 3, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Toru Mitsuki
  • Micro-machined electromechanical sensors (MEMS) devices
    Patent number: 6768181
    Abstract: Micro-machined electromechanical sensor (MEMS) devices having feature orientation delicately adjusted after initial formation and installation within the device packaging to trim one or more performance parameters of interest, including modulation, bias and other dynamic behaviors of the MEMS devices.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: July 27, 2004
    Assignee: Honeywell International, Inc.
    Inventor: Paul W Dwyer