Abstract: A crystallization method includes forming a black matrix layer that absorbs external light on an insulating substrate, wherein an upper region of the black matrix layer comprises a catalyst for silicon crystallization, patterning the black matrix layer, forming an amorphous silicon thin film on the insulating substrate and the black matrix layer, and thermally processing the amorphous silicon thin film for crystallization. A thin film transistor formed using the crystallization method has improved properties as a continuous metal-induced crystallization region and a metal-induced lateral crystallization region are formed therein without a definite boundary.

Abstract: A high speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided.

Abstract: Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindrical field effect devices are disclosed to exemplify the use of the pedestals and/or sidewalls. A system for forming the pedestals and sidewalls is described.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.

Abstract: To form metal interconnections in a flash memory device, the gate of the peripheral region is etched to form a first contact hole on a substrate. Silicon nitride and first oxide films are formed on the gate including the first contact hole. The first oxide film is etched to expose the source and filled by a first plug. A second oxide film is formed and etched with the first oxide films to form second contact holes exposing the drain, the source, and the first contact hole that are filled by second plugs. A third oxide film is formed and etched to form third contact holes exposing the first and second plugs and a portion of the second oxide film corresponding to the drain. The second and first oxide films are etched to form fourth contact holes exposing the first and second plugs and the drain. Metal interconnections fills the fourth contact holes.

Abstract: Before a semiconductor chip (2) is mounted on package board (5), an insulating layer (3) is formed on the reverse side of the semiconductor chip (2) for preventing insulation failures. If the insulating layer (3) is formed by applying an insulating film, then the insulating layer (3) reliably achieves a predetermined thickness for reliable electric insulation and can easily be formed. The semiconductor chip (2) with the insulating layer (3) formed thereon is fixed to the package board (5) which has surface interconnections (7) by an insulating adhesive (adhesive layer 4). The semiconductor chip (2) and the surface interconnections (7) are insulated from each other by the insulating layer (3). Therefore, the adhesive may be used in a minimum quantity. Since the semiconductor chip (2) can be pressed under an increased pressure, the semiconductor chip (2) is reliably joined to the package board (5).

Abstract: In accordance with the objectives of the invention a new method is provided for ESD protection of mounted flip chips. In a first embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad. The substrate of the flip chip package interconnects all of the dedicated bump pads, completing the ESD network. Under the second embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad, a last metal layer interconnects all of the dedicated bump pads, completing the ESD network.

Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.

Abstract: As an opening exposing a surface of an element-forming region positioned in a region lying between two gate electrodes, a first opening is formed based on a resist pattern formed such that a portion of a region where the opening is formed overlaps two-dimensionally with a portion of one gate electrode. As an opening exposing a surface of one gate electrode, a second opening is formed based on a resist pattern formed such that a region where the opening is formed overlaps two-dimensionally solely with one gate electrode. Here, the first opening is covered with a non-photosensitive, organic film and the resist pattern. Thereafter, a tungsten interconnection is formed in the first and second openings. Thus, a semiconductor device, of which production cost is reduced, and in which electrical short-circuit and falling off of an interconnection are suppressed, can be obtained.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first co

Abstract: A MOS-gated semiconductor device is shown and described which includes deep implanted junctions and thick oxide spacers disposed over a substantial portion of common conduction regions.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: A micro-scale interconnect device with internal heat spreader and method for fabricating same. The device includes first and second arrays of generally coplanar electrical communication lines. The first array is disposed generally along a first plane, and the second array is disposed generally along a second plane spaced from the first plane. The arrays are electrically isolated from each other. Embedded within the interconnect device is a heat spreader element. The heat spreader element comprises a dielectric material disposed in thermal contact with at least one of the arrays, and a layer of thermally conductive material embedded in the dielectric material. The device is fabricated by forming layers of electrically conductive, dielectric, and thermally conductive materials on a substrate. The layers are arranged to enable heat energy given off by current-carrying communication lines to be transferred away from the communication lines.

Abstract: Contact openings in semiconductor substrates are formed through insulative layers using an etchant material. The etchant typically leaves behind a layer of etch residue which interferes with the subsequent deposition of conductive material in the opening, as well as the conductive performance of the resulting contact. A method of etch removal from semiconductor contact openings utilizes ammonia to clean the surfaces thereof of any etch residue.

Abstract: Formation of elements of a vertical transistor is described, particularly, a gate-source-drain arrangement of a CMOS transistor. Vertical transistors are used frequently in the integrated circuit art. Accordingly, improved methods for their formation, which are not limited by constraints of photolithography, have great utility and importance. Those of skill in the art will appreciate that the techniques described may be used to fabricate other types of devices as well. For example, junctions of a bipolar transistor (as well as other device junction types) may be fabricated using the methods described herein.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of both hydrogen and fluorine as process gases in the reactive mixture of a plasma-containing CVD reactor. The process gas also includes dielectric forming precursors such as silicon and oxygen-containing molecules.

Abstract: A vapor-phase growth method for forming a boron-phosphide-based semiconductor layer on a single-crystal silicon (Si) substrate in a vapor-phase growth reactor. The method includes preliminary feeding of a boron (B)-containing gas, a phosphorus (P)-containing gas, and a carrier gas for carrying these gases into a vapor-phase growth reactor to thereby form a film containing boron and phosphorus on the inner wall of the vapor-phase growth reactor; and subsequently vapor-growing a boron-phosphide-based semiconductor layer on a single-crystal silicon substrate. Also disclosed is a boron-phosphide-based semiconductor layer prepared by the vapor-phase growth method.

Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.