Abstract: A power semiconductor device includes a portion and an external package enclosing the portion. The portion includes a ceramic board sides provided on the ceramic board defining a space filled with a thermal insulator, and a silicon carbide power semiconductor element enclosed within the thermal insulator. The external package is made of a material having a thermal conductivity lower than that of the side.

Abstract: A drain loaded 1T1R resistive memory device and 1T1R resistive memory array are provided. The resistive memory array comprises an array of drain loaded 1T1R resistive memory device structures. Word lines are connected across transistor gates, while a resistive elements are connected between transistor gates and bit lines. The resistive element comprises a material with a resistance that is changed electrically, for example using a sequence of electric pulses. The resistive element may comprise PCMO.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: The present invention provides a structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which comprises a SOI (Silicon-On-Insulator) device, a MOS (Metal Oxide Semiconductor) formed on said SOI device, and a metal-silicide layer. Said SOI device includes a substrate, an insulation layer formed on said substrate, and a silicon layer formed on said insulation layer, and the MOS is formed on said SOI device. The metal-silicide layer is formed in accordance with a metal aligned process by a metal layer being deposited on said SOI device and on said MOS for reacting with said silicon layer, and an implant-to-silicide process is employed to form a high-density source region and a high-density drain region for modifying Schottky Barrier and diminishing Carrier Injection Resistance.

Abstract: A method of sealing an optical fiber in a microchip includes providing a device microchip, a top microchip and an optical fiber; forming a groove in at least one of the device microchip and the top microchip; coating metal on the optical fiber; depositing metal on the groove and top surfaces of the device microchip and the top microchip; depositing solder on the top surface of at least one of the device microchip and the top microchip; placing the optical fiber in the groove; placing the top microchip on the device microchip; and reflowing the solder to form a hermetic seal.

Abstract: A method for forming an LDNMOS (1) and LDPMOS (2) in a CMOS process comprises forming the LDNMOS (1) and LDPMOS (2) to a stage where a gate (14) is laid down on a gate oxide layer (12) and a locos (9) is formed over the respective N and P-wells (4) and (5) of the LDNMOS (1) and LDPMOS (2). A P-body (15) is formed in the N-well (4) of the LDNMOS (1) by implanting a boron dopant in two stages, in the first stage at a first tilt angle (&thgr;) of 45° for forming the P-body (15) beneath the gate (14) for determining the source/drain threshold voltage, and subsequently at a second tilt angle (&phgr;) of 7° for extending the P-body (15) downwardly at (25) for determining the punchthrough breakdown voltage of the LDNMOS (1). The formation of an N-body (16) in a P-well (5) of the LDPMOS (2) is similar to the formation of the P-body (15) with the exception that the dopant is a phosphorous dopant.

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract: A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.

Abstract: A dicing method for a micro electro mechanical system chip, in which a high yield and productivity of chips can be accomplished, resulting from preventing damage to microstructures during a dicing process by using a protective mask. The dicing method for a micro electro mechanical system chip, comprising the steps of designing a grid line and wafer pattern on a chip-scale on the non-adhesive surface of a transparent tape as a protective mask (first step); sticking microstructure-protecting membranes on the adhesive surface of the transparent tape (second step); putting the transparent tape on the whole surface of a wafer in a state wherein the grid line designed on the non-adhesive surface of the transparent tape is matched to the dicing line of the wafer (third step); cutting the transparent tape to a size larger than the wafer, mounting the wafer on a guide ring and dicing the wafer (fourth step); and separating the transparent tape from diced chips (fifth step).

Abstract: The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate.

Abstract: An optical device includes a substrate, dielectric layers disposed on portions of the substrate, and a piezoelectric layer disposed over the substrate and the dielectric layer, wherein the piezoelectric layer functions as a waveguide in which incident light is transmitted parallel to the surface of the piezoelectric layer. The piezoelectric layer has first piezoelectric layer regions each having an axis orientation directed to a first direction depending on the substrate and second piezoelectric layer regions each having an axis orientation directed to a second direction depending on the dielectric layers, and each of the first piezoelectric layer regions and each of the second piezoelectric layer regions are adjacent. A method manufacturing an optical device includes the steps of forming dielectric layers on portions of a substrate, and forming a piezoelectric layer over the dielectric layers and the substrate.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: Nanowire devices may be provided that are based on carbon nanotubes or single-crystal semiconductor nanowires. The nanowire devices may be formed on a substrate. Catalyst sites may be formed on the substrate. The catalyst sites may be formed using lithography, thin metal layers that form individual catalyst sites when heated, collapsible porous catalyst-filled microscopic spheres, microscopic spheres that serve as masks for catalyst deposition, electrochemical deposition techniques, and catalyst inks. Nanowires may be grown from the catalyst sites.

Abstract: A TFT-LCD device has a plurality of scanning lines formed by a first level metallic layer, a plurality of data lines formed by a second level metallic layer, and an array of pixels each having a TFT and a pixel electrode made of a third level ITO layer. Each pixel further includes a shied ring formed by the second level metallic layer for suppressing variance in the parasitic capacitances formed between the pixel electrode and other conductive layers. The suppression of the variance in the parasitic capacitances reduces the feed-through voltage, thereby improving the display performance of the TFT-LCD device.

Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.

Abstract: There is provided a structure of a pixel TFT (n-channel type TFT) in which an off current value is sufficiently low. In impurity regions, a concentration distribution of an impurity element imparting one conductivity type is made to have a concentration gradient, the concentration is made low at a side of a channel formation region, and the concentration is made high at the side of an end portion of a semiconductor layer.

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

Abstract: An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment mark structure (22) is provided. The features of the alignment mark structure (22) are formed in an alignment mark region (20) concurrently while features for a circuit region having vertical gate transistors are being formed. There are no extra or added processing steps added for forming the alignment mark structure (22) because it is formed concurrently while forming features in the circuit region. The resulting alignment mark structure (22) has step features (62) so that the step features (62) can be seen after the opaque material layer (88) covers the alignment mark structure (22).

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.