Abstract: A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature or phase shifted low aspect primary features.

Abstract: An etching solution for etching one of a copper single metal layer and a copper (Cu)/titanium (Ti) double metal layer that serves as one of a gate electrode, a source electrode, and a drain electrode of a thin film transistor for a liquid crystal display (LCD) device includes oxone, fluoric compounds, one of a reducing agent and a weak oxidizing agent, an etching rate restrainer, KHF2, and water.

Abstract: The invention relates to a device and method for automatically determining the surface quality of a bonding interface between two wafers. The device includes a detector for automatically detecting a bonding wave at a predetermined measuring site to determine when bonding occurs at the measuring site, and a processing unit for automatically calculating the bonding speed based on a location of the measuring site and at least one other predetermined site.

Abstract: This specification describes techniques for fabricating connections between pairs of components. Each connection includes an array of bumps on a male component, and a matching array of wells filled with bonding material on a female component. The bump/well connections can be spaced with a pitch of less than 100 microns. One application of the invention is the attachment of electronic components to interconnection circuits or circuit assemblies to form electronic modules. The electronic components may be IC chips or high-density interconnect cables. Another application is alignment of optical components. The direct chip attachment techniques are described in the context of fabrication, assembly, test, rework, and cooling of electronic modules employing flip chip components. The preferred method is to fabricate the module on a glass carrier using a release layer so that the carrier can be removed after most of the processing is done.

Abstract: Etching in combination with other processing techniques is used to facilitate alignment of an optical die in an optical system. The optical dies are formed on a wafer level and need to be singulated for use in the optical system. The formation of a precise edge from etching allows more accurate alignment of the optical die in the optical system. The other processing techniques include dicing, sawing, cleaving, breaking and thinning.

Abstract: A method of manufacturing a light emitting semiconductor package, the method comprising the steps of: obtaining a semiconductor wafer 252 which includes a plurality of light emitting devices 254 residing on or in a surface of the semiconductor wafer 252; forming at least one first hollow cap 256, each first hollow cap 256 formed to provide: a central portion 260 and first perimeter walls extending from the perimeter edge of the central portion with the free edges of the first perimeter walls adapted to be bonded to the surface of the semiconductor wafer 252 to provide a first cavity; at least one region 258 of the central portion 260 which is substantially transparent or translucent to electromagnetic radiation; bonding the at least one first hollow cap 256 to the semiconductor wafer 252, the central portion overlying at least one of the plurality of light emitting devices 254; and, separating the semiconductor wafer 252 with bonded caps 256 into light emitting semiconductor packages 250.

Abstract: Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: The invention concerns a method for fabricating a damascene type structure of interconnections on a semiconductor device. It includes the following steps: formation of a first level of conductors in a first electric insulating layer and of a second level of conductors in a second electric insulating layer, with the conductors in the first level being arranged with a pre-determined spacing in order to allow, in a later step, the formation of air or vacuum gaps between the conductors in the first level, elimination of the second electric insulating layer, elimination, at least partial, of the first electric insulating layer in order to eliminate at least some parts of the first layer corresponding to the gaps to be formed, deposit, over the structure thus obtained, of a material with low permittivity, with this deposit not filling the space between the conductors in the first level whose spacing has been planned to allow the formation of gaps.

Abstract: A method for forming arrays of metal, alloy, semiconductor or magnetic clusters is described. The method comprises placing a scaffold on a substrate, the scaffold comprising, for example, polynucleotides and/or polypeptides, and coupling the clusters to the scaffold. Methods of producing arrays in predetermined patterns and electronic devices that incorporate such patterned arrays are also described.

Abstract: Methods are presented, in which an oxide protection layer is provided on a gate structure for protection against poly mushrooming during selective epitaxial silicon deposition in fabricating elevated or recessed source transistors. In one implementation, the protection layer is constructed by depositing silicon germanium over a gate polysilicon layer prior to gate patterning, and oxidizing the device to form a silicon germanium oxide over the gate polysilicon. The protection layer is then removed following selective epitaxial deposition.

Abstract: In a method of transferring semiconductor chips from a substantially flat wafer having an active side with a plurality of individual semiconductor chips formed thereon and a support side opposite the active side to a receiver, and the wafer is attached with its support side by way of an adhesive sheet to a support structure and is cut into segments corresponding to the individual semiconductor chips so that the semiconductor chips are individually supported on the adhesive sheet with their active sides exposed and facing away from the adhesive sheet, the support structure is moved with the individual semiconductor chips into a position wherein a particular semiconductor chip to be removed is positioned in a removal location above a receiver and the adhesive sheet is pushed downwardly at the particular semiconductor chip location so as to release the particular semiconductor chip and transfer it with the active side thereof onto the receiver.

Abstract: A silylation treatment unit includes a chamber, a heating mechanism provided in this chamber for heating a substrate, a supplying mechanism for supplying a vapor including a silylation reagent into the chamber. The unit also has a substrate holder for holding the substrate in the chamber, in which an interval between the heating mechanism and the substrate is adjustable to at least three levels or more. The substrate is received such that it is least influenced by a heat in the chamber by maximizing the interval from the heating mechanism. The interval is brought comparatively closer to the heating mechanism to wait until the temperature inside the chamber obtains a high planer uniformity. The interval is brought further closer to the heating mechanism after a high planer uniformity is obtained such that a silylation reaction occurs.

Abstract: A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer.

Abstract: A first trench is formed in a surface of an n+-type semiconductor substrate that forms a source region. A p-type base region, an n?-type drift region, and an n+-type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n+-type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.

Abstract: A method of manufacturing a metal oxide semiconductor. A gate structure of the metal oxide semiconductor is etched. A nitrogen-comprising gas, which may be NO or N2O, is made to flow over the metal oxide semiconductor. A pre-implant film is grown over the edges of the gate structure. The pre-implant film may repair damage to a gate stack edge caused by an etching process. The film may be substantially silicon nitride. Beneficially, such a film may be thinner than a conventional silica oxide film. A thinner film does not deleteriously contribute to non-uniformities in a tunnel oxide. A non-uniform tunnel oxide may result in a non-uniform field between a gate and a channel. Non-uniform fields may have numerous deleterious effects. Advantageously, embodiments of the present invention overcome prior art deficiencies in repairing gate stack edge defects.

Abstract: In a thermal processing apparatus irradiating a substrate with light from a lamp for heating the substrate, an opening is formed in a reflector for mounting a camera unit. The camera unit images three portions of an auxiliary ring supporting the substrate, for obtaining the position of the center of the auxiliary ring before the thermal processing apparatus receives the substrate therein. The camera unit further images the substrate for obtaining the position of the center of the substrate before the thermal processing apparatus receives the substrate therein and places the same on the auxiliary ring. The thermal processing apparatus moves the substrate so that the center thereof coincides with the center of the auxiliary ring, and thereafter places the former on the latter.

Abstract: In one embodiment, the invention provides a method comprising supporting a plurality of active electronic components on a first wafer; shaping a second wafer to define a plurality of spaces, each to accommodate one of the active electronic components when the second wafer is aligned and brought into face-to-face contact with that first wafer in a contact position; moving the second wafer into the contact position; and bonding the second wafer to the first wafer in the contact position.

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A multiprocessor integrated circuit is disclosed. A preferred embodiment of a multiprocessor chip has microprocessors formed on silicon-on-insulator regions and dynamic random access memory level-2cache memories or level-3 cache memories formed on bulk regions of the chip. A preferred embodiment includes a redundant architecture having a signal bus for coupling the microprocessors to the level-2 or level-3 cache memories in which the signal bus includes a programmable selector circuit for bypassing defective microprocessors or defective level-2 or level-3 cache memories.