Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: A thin film transistor is disclosed, which includes an oxide semiconductor layer on a substrate; a gate insulating film on the oxide semiconductor layer; a gate electrode on the gate insulating film; a hydrogen supply layer on the gate insulating film; a source electrode connected with the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode and connected with the oxide semiconductor layer, wherein the oxide semiconductor layer includes a channel portion overlapped with the gate electrode and a connecting portion not overlapped with the gate electrode, a hydrogen concentration of the connecting portion is higher than that of the channel portion, and the gate insulating film includes a first area overlapped with the gate electrode and a second area not overlapped with the gate electrode, and a hydrogen concentration of the second area is higher that of the first area.

Abstract: A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions.

Abstract: An organic light emitting diode display includes a substrate, a first electrode, a second electrode, an organic emission layer positioned between the first electrode and the second electrode, a driving voltage line, a dummy electrode. The dummy electrode is positioned at the same layer as the first electrode.

Abstract: An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.

Abstract: A method for manufacturing a display substrate includes a step of forming a pattern of a barrier layer and a pattern of a first electrode. The step of forming the pattern of the barrier layer and the pattern of the first electrode includes: forming a barrier layer film and a first electrode film sequentially; and forming the pattern of the barrier layer and the pattern of the first electrode by a single patterning process.

Abstract: An organic light emitting diode display includes a plurality of first signal lines, a first insulating layer covering the first signal lines, a plurality of second signal lines on the first insulating layer and crossing the first signal lines, and a plurality of pixels connected to the first signal lines and the second signal lines. A groove in the first insulating layer is between adjacent ones of the pixels and a filling material in the groove.

Abstract: A first memory film and a sacrificial fill structure are formed within each first-tier memory opening through a first alternating stack of first insulating layers and first spacer material layers. A second alternating stack of second insulating layers and second spacer material layers is formed over the first alternating stack, and a second-tier memory opening is formed over each sacrificial fill structure. A second memory film is formed in each upper opening, and the sacrificial fill structures are removed from underneath the second-tier memory openings to form memory openings. A semiconductor channel is formed on each vertically neighboring pair of a first memory film and a second memory film as a continuous layer. The first memory film is protected by the sacrificial fill structure during formation of the second-tier memory openings.

Abstract: A light detection device includes: a Fabry-Perot interference filter provided with a light transmission region; a light detector configured to detect light transmitted through the light transmission region; a package having an opening and accommodating the Fabry-Perot interference filter and the light detector; and a light transmitting unit arranged on an inner surface of the package so as to close an opening, the light transmitting unit including a band pass filter configured to transmit light incident on the light transmission region. When viewed from a direction parallel to the line, an outer edge of the Fabry-Perot interference filter is positioned outside an outer edge of the opening, and an outer edge of the light transmitting unit is positioned outside the outer edge of the Fabry-Perot interference filter.

Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.

Abstract: A high voltage device may include a substrate, source and drain regions, a gate structure and an oxide layer. The substrate may include a recessed region with a recessed surface lower than a top surface of the substrate. The source and drain regions may be at least partially arranged within the substrate under the recessed surface and top surface respectively. The drain region may be positioned higher than the source region. The gate structure may include first and second portions arranged over the recessed region. The first and second portions may be nearer to the source and drain regions respectively. The oxide layer may include a first part between the first portion of the gate structure and the recessed surface, and a second part between the second portion of the gate structure and the recessed surface. The second part of the oxide layer may be thicker than the first part.

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.

Abstract: A method of forming an active matrix pixel that includes forming a driver device including contact regions deposited using a low temperature deposition process on a first portion of an insulating substrate. An electrode of an organic light emitting diode is formed on a second portion of the insulating substrate. The electrode is in electrical communication to receive an output from the driver device. At least one passivation layer is formed over the driver device. A switching device comprising at least one amorphous semiconductor layer is formed on the at least one passivation layer over the driver device.

Abstract: A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and/or metal one extension layers are placed in the identified external path.

Abstract: A quantum dot infrared detector includes a quantum dot-stacked structure in which quantum dot layers each containing quantum dots stacked on top of one another and intermediate layers. The quantum dots are sandwiched between the intermediate layers in the height direction of the quantum dots. The quantum dots have conduction band quantum confinement levels that include a conduction band ground level, a conduction band first excitation level at a higher energy position than the conduction band ground level, and a conduction band second excitation level at a higher energy position than the conduction band ground level. An energy gap between the conduction band first excitation level and the conduction band bottom of the intermediate layer and an energy gap between the conduction band second excitation level and the conduction band bottom of the intermediate layer are each smaller than twice thermal energy.

Abstract: Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

Abstract: A display device includes a substrate including a display area and a peripheral area surrounding the display area; a display element in the display area and electrically connected to a thin film transistor; a power supply line in the peripheral area; an insulating layer covering a portion of the power supply line; and a barrier layer on the insulating layer and including a first side surface facing the display area and a second side surface that is opposite to the first side surface, wherein at least one of the first side surface and the second side surface includes a concavo-convex surface, wherein the barrier layer forms a step difference with respect to an upper surface of the insulating layer, and an end of the insulating layer extends from the display area in a direction toward an edge of the substrate beyond the second side surface of the barrier layer.

Abstract: A III-nitride vertical field effect transistor comprises a base plate; a mask layer overlaying said base plate and having opening windows for partial exposure of said base plate; a drain grown epitaxially onto regions of said base plate exposed by the opening windows of said mask layer; an insulation layer grown epitaxially onto said drain; a source grown epitaxially onto said insulation layer; a vertical nitride stack grown epitaxially onto the side faces of said drain, said insulation layer and said source, overlaying said mask layer and providing at least one vertical conducting channel to connect said source to said drain; a current flowing from said source to said drain through a conducting channel can be modulated by an electrical voltage that is applied to the side face of said vertical nitride stack. There are preferably also electrodes and edge terms.

Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.