Patents Examined by Cynthia Britt
  • Patent number: 11181578
    Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11177015
    Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, INC.
    Inventors: Nidhi Sinha, Garima Sharda, Dinesh Joshi, Akshay Pathak
  • Patent number: 11175339
    Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1141.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1141.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1141.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1141.1 circuitry in the interposer with 1141.1 circuitry in the die of the stack.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11171742
    Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 9, 2021
    Assignee: Futurewei Technologies, Inc.
    Inventors: Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko, Pavel Anatolyevich Panteleev, Elyar Eldarovich Gasanov, Aleksey Alexandrovich Letunovskiy, Wen Tong, Carmela Cozzo
  • Patent number: 11156664
    Abstract: Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Yisu Hai, Jonguk Song
  • Patent number: 11157354
    Abstract: A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 26, 2021
    Inventors: Jong Pil Son, Sin Ho Kim
  • Patent number: 11150299
    Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 19, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
  • Patent number: 11150297
    Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11152954
    Abstract: A decoding method is provided, and the method includes performing a decoding operation on a plurality of data bit value sets of a codeword. The decoding operation includes following steps: (1) obtaining a syndrome of the data bit value sets; (2) determining whether the codeword is correct or incorrect according to the latest obtained syndrome, wherein if the codeword is correct, the decoding operation is ended, wherein if the codeword is wrong, continuing to step (3) to start an iterative operation; (3) obtaining a plurality of error value sets respectively corresponding to the data bit value sets, wherein in response to obtaining a first error value set, steps (4) and (5) are performed simultaneously; (4) performing an extreme value search operation; (5) performing a bit-flipping operation; and (6) performing a syndrome calculation operation after the step (5) is completed, and performing step (2).
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 19, 2021
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Ting-Ya Yang, Yuan-Syun Wu
  • Patent number: 11144696
    Abstract: The translation based test architecture translates inputs, test control signals, and the chip pin IOs. Translation of test control signals derives dedicated local test control signals for each individual circuit-under-test (CUT) can introduce programmability directly into the test pattern transformation and composition. Using the local test control signals realizes a diversified test functions in each individual CUT without increasing test resource requirement. The translation of IO enable signals of chips can be used to create test scenarios in multi-chip module systems. Transformation of the generated test patterns to derive new test patterns occurs by retranslation of the signals within the generated test patterns. The retranslation can be reassigning test data of the translation layer cells in the generated test patterns and adjustment of corresponding difference in the test patterns. To achieve retranslation, the translation layer cells are identified in the test patterns.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 12, 2021
    Inventor: Chinsong Sul
  • Patent number: 11138083
    Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf H. Kuehnis, Enrico D. Carrieri
  • Patent number: 11137447
    Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11137448
    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11132255
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 11125818
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11128282
    Abstract: A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: September 21, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sergio Nicolás Deligiannis, Lucas Intile, Florencia Ferrer
  • Patent number: 11119857
    Abstract: An integrated circuit (IC) chip for transparent and in-service or production repair of single to multiple memory cell defects in a word during the datapath transit of the word between core memory to the interface of the IC via capturing an accurate bit from a word during a write access to a known defective memory address, and by substituting in a non-defective bit into the word during a read access from a known defective memory address. The IC includes: address matching circuit (CAM), a random access memory (RAM) of substitute memory cells containing accurate associated bit data and bit location in word of defect, and data selection circuitry (MUXs) coupled together.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: September 14, 2021
    Assignee: MOSYS, INC.
    Inventors: Dipak K Sikdar, Rajesh Chopra
  • Patent number: 11112457
    Abstract: A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mary P. Kusko, Franco Motika, Eugene Atwood
  • Patent number: 11112458
    Abstract: During a test for integrated circuit aging effects, contents of a first set of flip flop circuits are transferred to a second set of flip flop circuits. A first test value is applied to inputs of a combinatorial logic circuit and outputs from the combinatorial logic circuitry are provided to inputs of the first set of flip flop circuits. The combinatorial logic circuitry is reversible and conservative. The outputs from the first flip flop circuits are compared to the first test value to determine if there is a match. A second test value is applied to the inputs of the combinatorial logic circuitry and the outputs from the combinatorial logic circuitry are provided to inputs of the first set of flip flop circuits. The outputs from the first flip flop circuits are compared to the second test value to determine if there is a match, and when the test mode finishes, contents of the second set of flip flop circuits are transferred to the first set of flip flop circuits.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: September 7, 2021
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 11105853
    Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, Richard Frank Rizzolo, Paul Jacob Logsdon