Patents Examined by Cynthia Britt
  • Patent number: 10348328
    Abstract: Programming of frozen bits of first stage control channel information block enables scheduling information to be included for the second stage of the control channel information. By including some of the scheduling information for the second stage in the first stage frozen bits, the size of the first stage information blocks can be reduced, reducing the overhead required to transmit control information for the traffic channel. In an embodiment, the frozen bits can convey scheduling information that is lower priority than the scheduling information conveyed in the non-frozen bits of the first stage control channel information block. In another embodiment, the frozen bits can include parity bits, or cyclic redundancy check bits that are masked with the scheduling information.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 9, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Xiaoyi Wang, Arunabha Ghosh
  • Patent number: 10345380
    Abstract: A method and circuit are provided for implementing enhanced scan data testing with over masking removal in an on product multiple input signature register plus (OPMISR+) test due to common Channel Mask Scan Registers (CMSRs) loading, and a design structure on which the subject circuit resides. An OPMISR plus satellite includes a multiple input signature register (MISR) for data collection and a plurality of associated scan channels. A common Channel Mask Scan Registers (CMSR) logic is used with the multiple input signature register (MISR). Unique CMSR data is loaded into at least one OPMISR plus satellite for implementing enhanced scan data testing. Scan pausing is used to reduce the amount of CMSR scan load data by loading the unique CMSR data only when needed.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Matthew B. Schallhorn, Mary P. Kusko, Amanda R. Kaufer, Michael J. Hamilton
  • Patent number: 10339004
    Abstract: A controller including: an initialization unit initializing values and states of variable nodes and initializing values of check nodes; a variable node update unit updating the values and states of the variable nodes; a check node update unit updating the values of the check nodes based on the updated values and states of the variable nodes; and a syndrome check unit deciding iteration of the operation of the variable node update unit and the check node update unit when the values of the check nodes are not all in a satisfied state, the variable node update unit calculates reliability values of the variable nodes and a reference flip value based on a result of a previous iteration, and the variable node update unit updates the values and states of the variable nodes based on the reference flip value and the reliability values and states of the variable nodes.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Soon-Young Kang
  • Patent number: 10330729
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 25, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10331517
    Abstract: Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Jungwon Suh
  • Patent number: 10333560
    Abstract: A node (110, 115) receives (804) transmissions associated with a given set of information bits, wherein each of the transmissions use a different polar code and share one or more information bits of the given set of information bits. The node determines (808), at each of a plurality of polar decoders (505, 605) of the node, soft information for each information bit included in an associated one of the transmissions, wherein each of the plurality of polar decoders is associated with a different transmission of the transmissions. The node provides (812), from each polar decoder of the plurality to one or more other polar decoders of the plurality, the determined soft information for any information bits shared by their respective associated transmissions, and uses (816) the provided soft information in an iterative decoding process to decode one or more of the received transmissions.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Mattias Andersson, Yufei Blankenship, Ivana Maric
  • Patent number: 10326550
    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 18, 2019
    Assignee: INPHI CORPORATION
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja
  • Patent number: 10318210
    Abstract: Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 11, 2019
    Assignee: SONY CORPORATION
    Inventor: Ken Ishii
  • Patent number: 10320419
    Abstract: An encoding method, decoding method, encoding device and decoding device for structured LDPC codes. The method includes: determining a basic matrix used for encoding, which includes K0 up-and-down adjacent pairs; and according to the basic matrix and an expansion factor corresponding to the basic matrix, performing an LDPC encoding operation of obtaining a codeword of Nb×z bits according to source data of (Nb?Mb)×z bits, herein z is the expansion factor, and z is a positive integer which is greater than or equal to 1. The provided technical solution is applicable to the encoding and decoding of the structured LDPC, thereby realizing the encoding and decoding of LDPC at the high pipeline speed.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: June 11, 2019
    Assignee: ZTE Corporation
    Inventors: Jun Xu, Liguang Li, Zhifeng Yuan, Jin Xu, Kaibo Tian
  • Patent number: 10320422
    Abstract: The present invention provides a coding method and a coding device. The coding method includes: coding information bits a to be coded via cyclic redundancy check CRC, then inputting the bits coded via the CRC into an interleaver determined by a construction parameter of a Polar code, where the interleaver is configured to interleave the bits coded via the CRC and output interleaved bits; and coding the output interleaved bits via the Polar code to obtain a coded Polar code. The above method is used to solve a problem in the prior art that minimum code distance of a Polar code is not large enough when the Polar code is relatively short or is of a medium length.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 11, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hui Shen, Bin Li
  • Patent number: 10318379
    Abstract: A decoding method is provided according to an exemplary embodiment. The method includes: reading first data and second data from a rewritable non-volatile memory module according to a read command; generating a re-read data set if a default decoding operation performed for the first data and the second data respectively fails; reading a to-be-decoded data set from the rewritable non-volatile memory module according to the re-read data set, and performing a first decoding operation for the first data based on the to-be-decoded data set; removing identification information corresponding to the second data from the re-read data set and storing the corrected second data if the second data is corrected in the first decode operation; and transmitting the corrected first data and the corrected second data to a host system.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Luong Khon
  • Patent number: 10310924
    Abstract: A read reclaim method of a storage device includes detecting, at a cycle of a random number of read operations, the number of error bits within non-selection data stored in each of a plurality of memory blocks. A memory block having the number of detected error bits, with respect to the number of read operations, increasing at a rate greater than a reference rate over one or more cycles of the random number of read operations is selected as a weak block. The number of error bits within non-selection data stored in the weak block is detected at a cycle of a fixed number of read operations. A detection is made of whether the number of error bits detected according to the fixed-number cycle is greater than or equal to a read reclaim reference. The non-selection data is data not requested by a host.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seung Jei, Heewon Lee, Suejin Kim
  • Patent number: 10313053
    Abstract: The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 4, 2019
    Assignee: Myriota Pty Ltd
    Inventors: Alexander James Grant, Andre Pollok, Gottfried Lechner, David Victor Lawrie Haley, Robert George McKilliam, Ingmar Rudiger Land, Marc Pierre Denis Lavenant
  • Patent number: 10312948
    Abstract: A hybrid automatic repeat request (HARQ) transmitter in a communications system employing a HARQ process, wherein a primary codeword from an arbitrary forward error correction (FEC) code is sent over a communications channel and negatively acknowledged by a HARQ receiver, includes a polar code retransmission apparatus. A primary codeword buffer stores the primary codeword, and a systematic incremental redundancy (IR) encoder receives a first segment of the primary codeword and encodes the first segment into a first IR codeword. The first segment of the primary codeword excludes at least one symbol of the primary codeword, and the systematic IR encoder comprises a systematic polar encoder. Primary codeword segments, received in response to decoding errors, are encoded into IR codewords, with a kth segment xSk of the primary codeword is excluded from retransmission of the kth IR codeword and the IR codewords may be permuted before transmission.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 4, 2019
    Assignee: Polaran Yazilim Bilisim Danismanlik Ithalat Ihracat Sanayi Ticaret Limited Sirketi
    Inventor: Erdal Arikan
  • Patent number: 10302695
    Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 28, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Akshat Jain
  • Patent number: 10303542
    Abstract: A semiconductor device includes a bitwise operation unit and a storage control unit. The bitwise operation unit performs a bitwise operation on first n-bit (n is an integer) data that is storage object data and second data of an n-bit bit pattern and generates third data of a bit pattern that the number of “1s” and the number of “0s” are almost the same as each other. The storage control unit stores the third data into a first storage destination of a storage unit and stores fourth data that is the third data or data that is converted into the third data by performing a bitwise operation that has been predetermined in advance on the data into a second storage destination of the storage unit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinichi Suzuki
  • Patent number: 10303545
    Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, Christian Jacobi, Barry M. Trager
  • Patent number: 10295597
    Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichi Maeda, Jun Matsushima, Hiroki Wada
  • Patent number: 10298261
    Abstract: Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 21, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Majid Nemati Anaraki, Xinde Hu, Richard David Barndt
  • Patent number: 10291355
    Abstract: An embedded system may include an embedded device and a host device. The embedded device may provide a packet for a service, and generate a first transmission control protocol (TCP) segment including a piece of the packet and a first header with no checksum value. The host device may receive the first TCP segment, generate a second TCP segment including the piece of the packet and a second header with a checksum value based on the piece of the packet and the first header, and generate an Internet protocol (IP) packet based on the second TCP segment.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventor: Stephen J. Silva