Patents Examined by Cynthia Britt
  • Patent number: 10802534
    Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Patent number: 10802908
    Abstract: Various method and apparatus embodiments for data dependent error correction code (ECC) encoding are disclosed. In one embodiment, a data object may include multiple portions, with each portion having different characteristics. An ECC encoder may allocate error correction resources (e.g., parity bits) to the different portions at respectively different data rates (e.g., more error correction resources to some portions relative to other portions). Upon completion of the allocation, the data object and the associated error correction resources are forwarded to a storage medium for storage therein.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 13, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ofir Pele, Ariel Navon, Alex Bazarsky
  • Patent number: 10795835
    Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 6, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10784900
    Abstract: A rate matching method for a polar code is provided, to improve performance. The method includes: encoding, based on an N*N encoding matrix of a polar code, a sequence including N first bits, to generate a mother code including N second bits, where the N first bits are in a one-to-one correspondence with N rows in the encoding matrix in sequence, and the N second bits are in a one-to-one correspondence with N columns in the encoding matrix in sequence; determining N?M to-be-punctured second bits from the N second bits, where at least one first bit in N?M first bits participating in encoding of the N?M second bits belongs to the first M first bits in the N first bits, and the N?M first bits are fixed bits; and puncturing the N?M second bits, to obtain a target polar code including M second bits.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Gongzheng Zhang, Ying Chen, Rong Li, Chaolong Zhang, Yourui Huangfu, Huazi Zhang
  • Patent number: 10771195
    Abstract: Provided are an HARQ operation procedure and control method between a terminal and a base station. In the method, the terminal receives HARQ feedback bundling control information from the base station through RRC signaling and downlink control information (DCI), bundles HARQ feedbacks in response to reception results of one or more pieces of downlink data according to the HARQ feedback bundling control information, and transmits the bundled HARQ feedbacks. The base station extracts effective information from the HARQ feedback information on the basis of transmission subframe information and checks whether the terminal receives the downlink data, thereby enabling the terminal to transmit the HARQ feedbacks while minimizing uplink resources, and the base station to perform an HARQ operation by checking whether downlink data in each subframe has been successfully transmitted.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: September 8, 2020
    Assignee: KT CORPORATION
    Inventors: Juhee Kim, Ki-ho Lee, Ki-Tae Kim
  • Patent number: 10771094
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller determines a read voltage for first data encoded by a first encoding scheme, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter of the first encoding scheme, and a second parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, or (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Koji Horisaki
  • Patent number: 10762007
    Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 1, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10763895
    Abstract: A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: September 1, 2020
    Assignee: Synopsys, Inc.
    Inventors: Venugopal Santhanam, Lokesh Kabra
  • Patent number: 10756845
    Abstract: An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16 k mode or a 64 k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 25, 2020
    Assignee: PANASONIC CORPORATION
    Inventor: Mikihiro Ouchi
  • Patent number: 10756761
    Abstract: Disclosed are a method for dividing a carrying block of a Low Density Parity Check (LDPC) code and an apparatus therefor. The method for dividing a LDPC code of the present disclosure can obtain a high throughput by using a limited size of shifting network. Moreover, it is possible to prevent degradation in performance due to a minimum size of code block by performing shortening for a large size of code block while minimizing the number of code blocks. Furthermore, in selection of a minimum size of code block, since a minimum size of code block is selected on the basis of shortening for a relatively large size of code block, it is possible to increase the size of the minimum size of code block.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: August 25, 2020
    Assignee: LG Electronics Inc.
    Inventors: Kwangseok Noh, Bonghoe Kim, Jinwoo Kim, Ilmu Byun, Jongwoong Shin, Seunggye Hwang
  • Patent number: 10749629
    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: August 18, 2020
    Assignee: INPHI CORPORATION
    Inventors: Jamal Riani, Benjamin P. Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
  • Patent number: 10739402
    Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mudasir Shafat Kawoosa, Rajesh Mittal
  • Patent number: 10735138
    Abstract: A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 4, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko, Pavel Anatolyevich Panteleev, Elyar Eldarovich Gasanov, Aleksey Alexandrovich Letunovskiy, Wen Tong, Carmela Cozzo
  • Patent number: 10725103
    Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: July 28, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10725857
    Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shemmer Choresh, Tomer Tzvi Eliash
  • Patent number: 10719394
    Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise receiving data pieces from a plurality of channels of a non-volatile storage device, assembling the data pieces into one or more error correction code (ECC) encoded codewords, and triggering an ECC engine to decode a codeword to generate decoded data to be returned to a host when the codeword is assembled. Each codeword may have data pieces retrieved from different channels. Thus, a data unit containing one or more ECC codewords may be spread into multiple channels of a non-volatile storage device and access latency may be improved by accessing multiple channels in parallel. An averaging effect may be achieved for an ECC codeword and ECC failures may be reduced. Fast NANDs implementing the techniques disclosed herein may achieve ultra-fast access and response time while maintaining a high throughput.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 21, 2020
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Jie Chen, Zining Wu
  • Patent number: 10712387
    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 14, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Baher S. Haroun, Brian J. Lasher, Anjali Vij
  • Patent number: 10713113
    Abstract: A method is proposed for operating a solid state storage device. The method comprises: encoding information and frozen bits into polar encoded bits; storing the polar encoded bits; reading the polar encoded bits, wherein the read polar encoded bits include the frozen bits and unfrozen bits, and performing a SCL decoding. The SCL decoding comprises: providing a list of candidate decoding paths; duplicating the candidate decoding paths; determining a maximum list size indicative of an allowed maximum number of candidate decoding paths that can be contained in the list of candidate decoding paths; pruning at least one duplicated candidate decoding path according to the maximum list size, and including in the list of candidate decoding paths a number of non-pruned duplicated candidate decoding paths not higher than the maximum list size; and selecting a decoding path from the list of candidate decoding paths.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 14, 2020
    Inventor: Sabrina Barbato
  • Patent number: 10713116
    Abstract: A method for operating a solid state storage device comprising memory cells exhibiting respective threshold voltage distributions comprises: providing sets of frozen bits each one associated with a respective RBER estimate being estimated according to a respective shape of the threshold voltage distributions; determining a current value of operative parameter(s) affecting the shape of the threshold voltage distributions; based on the current value of the operative parameter(s), determining a current shape of the threshold voltage distributions; determining a current RBER estimate associated with the current shape of the threshold voltage distributions; selecting a current set of frozen bits associated with the current RBER estimate; encoding the information bits and the current set of frozen bits with a polar code; storing the polar encoded bits in selected memory cells; reading the stored polar encoded bits, and decoding them according to said current set of frozen bits.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: July 14, 2020
    Inventor: Sabrina Barbato
  • Patent number: 10705934
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra