Abstract: A method for detecting a two-qubit correlated dephasing error includes accessing a signal of a quantum system, where the quantum system includes a plurality of qubits. Every qubit has a nonzero rate of dephasing and some qubits have a nonzero rate of correlated dephasing. The signal further includes information about a matrix that includes diagonal elements and off-diagonal elements. The off-diagonal elements of the matrix are 2s-sparse. The method further includes performing randomized measurements of the off-diagonal elements of the matrix and recovering the matrix based on a direct measurement of the diagonal elements of the matrix.

Abstract: The disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. The at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. The at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. The at least one processor is also configured to perform a remediation action in response to detecting the mismatch. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: Encoding and decoding devices, methods and programs are disclosed. In one example, decoding is provided by dividing input data into data strings of N bits, the data strings including a first data string, calculating a running disparity for the data strings, determining whether the first data string is to be inverted based upon the calculated running disparity, setting a flag for the first data string to a first value when it is determined that the first data string is not to be inverted, and setting the flag for the first data string to a second value and inverting the first data string when it is determined that the first data string is to be inverted, and outputting the first data string. The technology is, for example, applicable to a device communicating in an SLVS-EC specification.

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

Abstract: A transmission method includes creating an automatic repeat request process for a first packet; setting a lifetime for the automatic repeat request process; and sending the first packet; and when a preset retransmission condition in the lifetime of the automatic repeat request process is satisfied, retransmitting a second packet; where the preset retransmission condition includes that at least part of the time instants within the first predetermined time interval after an incorrect-reception acknowledgement frame returned by the receiver is received is beyond the lifetime of the automatic repeat request; where retransmitting the second packet includes: extending the lifetime of the automatic repeat request process to a third predetermined time interval following the first predetermined time interval, where the third predetermined time interval is at least a time period required for retransmitting the second packet; and retransmitting the second packet after the first predetermined time interval.

Abstract: A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding circuit having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.

Abstract: An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16 k mode or a 64 k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.

Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may identify a first set of bits associated with a first set of modulation layers. The wireless communication device may interleave a second set of bits associated with a second set of modulation layers to obtain an interleaved second set of bits. The wireless communication device may generate a combined set of bits based at least in part on combining the second set of bits and at least a portion of the first set of bits. The wireless communication device may perform a transmission based at least in part on the combined set of bits and the second set of bits. Numerous other aspects are described.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customer's system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: Various embodiments and implementations of graph-neural-network (GNN)-based decoding applications are disclosed. The GNN-based decoding schemes are broadly applicable to different coding schemes, and capable of operating on both binary and non-binary codewords, in different implementations. Advantageously, the inventive GNN-based decoding is scalable, even with arbitrary block lengths, and not subject to typical limits with respect to dimensionality. Decoding performance of the inventive GNN-based techniques demonstrably matches or outpaces BCH and LDPC (both regular and 5G NR) decoding algorithms, while exhibiting improvements with respect to number of iterations required and scalability of the GNN-based approach. These inventive concepts are implemented, according to various embodiments, as methods, systems, and computer program products.

Abstract: This application relates to a method for analyzing crosstalk between qubits, performed by a terminal. The method includes identifying a first qubit and a second qubit; performing spectral quantum process tomography on quantum states corresponding to the first qubit and the second qubit, to obtain a first eigenspectrum of a signal function corresponding to the first qubit and a second eigenspectrum of a signal function corresponding to the second qubit; performing spectral quantum process tomography on the quantum states corresponding to the first qubit and the second qubit, to obtain a third eigenspectrum of a common signal function of the first qubit and the second qubit; and determining a crosstalk intensity between the first qubit and the second qubit based on the first eigenspectrum, the second eigenspectrum, and the third eigenspectrum.

Abstract: A method for processing data stored in a memory unit. The method includes the following steps: ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit, forming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea.

Abstract: Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.

Abstract: A quantum system controller configured to perform (near) real-time quantum error correction is provided. The controller comprises a processing device comprising at least one first processing element; a time-indexed command (TIC) sequencer comprising at least one second processing element; and a plurality of driver controller elements configured to control the operation of respective components and associated with respective buffers and processing elements. The processing device is configured to generate commands and the TIC sequencer is configured to cause the time-indexed execution of the commands by the appropriate driver controller elements.

Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.

Abstract: A storage device includes a memory including a plurality of regions arranged along a first axis and a second axis orthogonal to each other, each of the plurality of regions belonging to one of first groups and one of second groups; and a controller configured to, when a programmed and weak region exists, put into a scan list on the basis of a weak list, a programmed and weak sub-region included in the programmed and weak region among the plurality of regions, put into the scan list, a first programmed and adjacent sub-region in a first programmed and adjacent region selected according to a second axis expansion order among the plurality of regions, and put into the scan list, a second programmed and adjacent sub-region in a second programmed and adjacent region selected according to a first axis expansion order among the plurality of regions.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.