Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

Abstract: The present technology relates to fused capacitor structures provided with a leadframe design configured to accepting a plurality of selectively placed fuses. The leadframe and fuse configuration enables construction of fused capacitors exhibiting low Equivalent Series Resistance (ESR) and allows construction of a variety of fuse configuration using a single leadframe design.

Abstract: A first CPU and a second CPU form a multi-CPU system which distributes processes related to data input-output and computation. Input-output devices such as an A/D converter and the like are connected to the first CPU through a bus. First and second serial communication circuits stand between the second CPU and the input-output devices of the A/D converter and the like to transmit and receive access demands from the second CPU to the input-output devices of the A/D converter and the like, and the demanded data. Also, the communication arbitration circuit stands between the first serial communication circuit and the first CPU to arbitrate access operations of the first CPU and of the second CPU to the input-output devices of the A/D controller and the like so that these access operations do not overlap.

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme.

Abstract: A disc controller divides write data supplied from a CPU into a plurality of data blocks and enables a common bus to be used for one disc unit and sends one of the data blocks obtained by the division. When the data block is received into a buffer 7 in the disc unit, the disc controller immediately enables the common bus to be used for another disc unit and sends the next data block and repeats the above operations, thereby dispersing and writing the write data to the disc units.

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals.

Abstract: A computerized switching system for coupling a workstation to a remotely located computer. A signal conditioning unit receives keyboard and mouse signals generated by a workstation and generates a data packet which is transmitted to a central crosspoint switch. The packet is routed through a crosspoint switch to another signal conditioning unit located at a remotely located computer. The second signal conditioning unit applies the keyboard and mouse commands to the keyboard and mouse connectors of the computer as if the keyboard and mouse were directly coupled to the remote computer. Video signals produced by the remote computer are transmitted through the crosspoint switch to the workstation. Horizontal and vertical sync signals are encoded on to the video signals to reduce the number of cables that extend between the workstation and the remote computer.

Abstract: In multimedia communications, a parent connection point and a Leg are generated for the communications resources of the first call, and a child connection point and a Leg are generated for the communications resources of a call subsequently generated and assigned the same call reference number. A Call object is generated to integrate the parent CP and the child CPs. The entire multimedia call is managed through the Call object and the Call object is generated and deleted by a parent connection point.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Abstract: An adapter which attaches Data Terminal Equipment (DTE) to a LAN includes a latch whose state is changed by conditions, such as a free token or a frame, on the LAN. The Output of the latch is used to calculate the bandwidth utilization of the LAN.

Abstract: The present application concerns a method and an apparatus, in a communication network, for processing the various fields of a protocol header preceding a data stream to provide a unique connection identifier for processing the data stream. All relevant protocol information is extracted from the protocol header for look up in a Content-Addressable Memory (CAM) (80). Each time an entry in the CAM (80) matches protocol information applied to the CAM's input (84), the CAM address of this storage section, i.e. the address of a row of the CAM (80), is provided at the output (82) thereof. The CAM addresses obtained from the protocol header are concatenated by means of a Connection Number Builder (CNB, 95) resulting in a unique connection identifier provided at the Protocol Filter's output (96) to be used for the processing of the data stream.

Abstract: A method and system for determining insertions and removals of floppy disks in a floppy disk drive. By monitoring states of a write protect signal, the present invention determines when floppy disks of a predetermined type are inserted into, and removed from, a floppy disk drive. More specifically, the present invention evaluates current states of the write protect signal in light of a default state of the write protect signal to determine when these floppy disks are inserted into, and removed from, the floppy disk drive.

Abstract: A method and apparatus of coordinating data transfer between hardware and software in a computer system through the use of a semaphore mechanism is disclosed. When a data packet is queued by preparing an entry in a data descriptor ring, software provides the descriptor entry number to a first storage field in a predetermined storage location which is accessible by hardware. Hardware accounts for the transactions it has completed by writing the descriptor entry number to a second storage field in the storage location. To determine if there is additional data to process, hardware compares the contents of the first storage field and the contents of the second storage field. If the contents of both storage fields are equal, the corresponding ring or channel has run out of data and no additional data is to be processed.

Abstract: A session-oriented local area network (LAN) application and an ISO 8802-2 protocol driver code will cooperate in a new form of connectionless, session-oriented communication called Sideband. At each session start-up time, the LAN Application will communicate with the enhanced ISO 8802-2 based protocol driver on the local system and the LAN Application and the 8802-2 based protocol driver on the remote system to determine if they all support the Sideband. If Sideband is fully supported by both systems, Sideband will be activated for the session. To communicate on a session which has Sideband active, the LAN Application requests that data is to be sent using the Sideband. A check is performed to see if the data meets Sideband criteria. As Sideband is a connectionless medium, the additional code path needed to set up and track timers and to handle the resend attempts are saved in the protocol.

Abstract: A method and apparatus to reduce bus usage and to increase resource locking protocol compatibility within a heterogeneous processing environment. Lock indicators are maintained in stores designated as lock registers and access to a resource is gained by any processor depending upon the status of a lock register associated with that resource. Access to a locked resource is barred to all but the locking processor, and only the processor which has set a lock can use or release that locked resource. A lock register controller controls the contents of the lock registers. A given processor P1-PN is identified by a unique ID vector G1-GN. These vectors are used to indicate both that a resource is locked and to indicate the identity of the locking processor. An unlocked resource is identified by a status vector (G.O slashed.).

Abstract: A computer system is provided including a processor and a parallel port configured to transfer data to or from a peripheral device. The parallel port includes a data buffer for receiving data transferred on a system bus when the processor executes a write cycle to the parallel port. A control unit associated with the parallel port decodes the address signals of the system bus to selectively latch data within the data buffer, and generates handshake signals to the peripheral device to indicate that write data is presently contained within the data buffer. The peripheral device consequently receives the data and provides an acknowledge signal to the control unit. The control unit thereafter generates a ready signal to indicate to the processor that the data has been written into the peripheral device.

Abstract: There is disclosed a variety of PC Card interfaces to interface from many different types of input devices to Personal Digital Assistants or palmtop computers through PCMCIA slots.The disclosed interfaces can receive data in undecoded format from laser based, wand based or CCD based barcode scanning engines, decode the data to alphanumeric characters and pass the decoded data to the PDA via the PCMCIA 68 pin bus. Other PC Card based interfaces are also disclosed which can accept input data in the form of ASCII or EBCDIC characters from virtually any type of input device which a standard serial or parallel output or custom output bus and input that data to the PDA through the PCMCIA bus.

Abstract: A method and system to eliminate service hardware previously provided with an adapter by providing a novel way to transfer its hardware service functions to a remote service hardware found elsewhere in a computer system, such as a mainframe. The transferred service controls include enabling the remote service hardware to control the updating of the adapter microcode; remotely control a recovery process for the adapter by remotely initializing its microcode, and remotely logging out and recovering from error conditions detected in the adapter; and remotely forcing a logout and recovery when the host OS detects a failure in the adapter. A standard I/O channel interface (optical or electronic) is provided between the adapter and an IOSS (Input Output Subsystem) of a computer system which has its own service processor element (SPE) used for servicing the computer system per se. The invention provides virtual service hardware for the adapter, but uses the SPE for its service hardware.

Abstract: The present invention which is an interactive communication system includes a specialized software or programming system to function in a general field known as intelligent tutoring, which is a promising means of delivering instructions on procedural skills relating to programming and like subjects. What has been developed is integrated distance learning tutor (IDLT) techniques involving the specialized programming, and which inexpensively integrates the concepts of "shared work space" and distance learning technology for a PC based intelligent tutoring systems.

Abstract: An apparatus and a method for using a host port to provide power to a level converter for voltage level conversion between a CMOS based palm-top computer and RS-232 host processor are disclosed. Energy from the host RS-232 port is extracted by the level converter from the request-to-send line (-12 V) and the data-terminal-ready line (+12 V). The host port request-to-send line may also be used to send a wake-up signal to turn on the palm-top computer. A momentary (1 millisecond) transition in the request-to-send line of the host port causes the level converter to present an appropriate signal on the wake-up pin of the palm-top computer.