Abstract: A data buffer that compensates the differences in data rates, between a storage device and an image compression processor. A method and apparatus for the real time indexing of frames in a video data sequence.

Abstract: An input/output request control system in a multi-processor system includes a plurality of information processing modules (PM). The system comprises a plurality of input/output adapters (ADP) commonly used by each of said information processing modules and a plurality of input/output devices (DVC) divided into groups, each group controlled by one of the input/output adapters. An input/output request maintaining table (LDVC) manages input/output requests from respective information processing modules for each of the input/output devices controlled by said information processing modules by using a queue. Input/output requests from respective information processing modules are processed based on the state of the input/output request maintaining table and the input/output devices.

Abstract: The present invention reduces the overhead commonly associated with computer queues by not requiring direct addressing of each location in the queue and by not requiring specialized underflow logic. Furthermore, reads and writes to the computer queue of the present invention can be asynchronous. Lastly, the computer queue of the present invention requires less circuitry and is thus physically smaller, requires less power to operate and can operate more quickly than can queues of the prior art.

Abstract: The present invention removes restrictions on the maximum data transfer rate provided by the Centronics.RTM. and PC-compatible parallel interface (i.e., standard parallel interface). Further, the present invention retains complete compatibility with the standard parallel port and peripheral device cable. With the present invention, a computer (i.e., host) is able to send data through a standard parallel port at a high rate by eliminating the Busy handshaking signal. Further, one to three Input/Output (I/O) instructions can be eliminated for each byte of data transfer.

Abstract: A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices requiring differing pixel rates. A clock circuit receives a pixel clock from a DAC, and generates a shift clock (VSCLK), a pipeline clock, and an input control signal, all of which are synchronized to the pixel clock. The pixel clock synchronizes color pixel data transfer from the MDI to the DAC. The pipeline clock synchronizes pixel data processing through a pixel processing pipeline according to the frequency of the pixel clock and the number of pixels processed in parallel through the pixel processing pipeline. The input control signal feeds the pixel data from a VRAM frame buffer into the pixel processing pipeline according to the pixel depth mode, the frequency of the pixel clock, and the number of pixels processed in parallel through the pixel processing pipeline.

Abstract: A system for securing communications between devices connected to a ring network. In accordance with the present invention, when a message frame is passed around the ring network, a gate keeper circuit associated with at least one port of a hub determines whether the message frame is intended for any of the nodes connected to that port. If the message frame is not intended for any of the nodes connected to that port, the message frame is encoded before it exits the hub through the port to traverse the subnetwork connected to the port, and decoded after it reenters the hub through the port. If and only if at least one node on the subnetwork connected to the port is intended to receive the message frame, then each node connected to that port can read the message frame.

Abstract: A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period.

Abstract: In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency.

Abstract: There is disclosed a two-wire input/output device with an object of avoiding that communication becomes impossible when an abnormality occurs on one of two-wire LAN transmission lines. A pair of buses are separately controlled by driver circuits. An abnormality on a transmission line is detected by an abnormality detecting circuit with data supplied to terminals, and driving of only one of the driver circuits which corresponds to the bus having the abnormality is stopped by an output control circuit. When an abnormality occurs on one of the transmission lines, communication is enabled with a driver circuit corresponding to the transmission line having the abnormality being protected.

Abstract: A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 b

Abstract: A register distributed across multiple single port adapters allows the system to operate the single port adapters identically to a single multi-port adapter. Each adapter has its own priority logic identical to the logic used on a multi-port adapter to select an individual port. The priority logic on the adapter allows the system to deselect one adapter and select another adapter in one operation. Each adapter has switch settings to allow selective control of individual bits on the system bus, which allows multiple adapters to respond to the processor simultaneously for different ports in the same manner as a multi-port adapter. By replying simultaneously, the system can use the same software to control two different hardware adapter types: single port, or multi-port.

Abstract: A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces.

Abstract: The level of an input signal to an interface is judged at a first threshold value and a second threshold value. The first threshold value and the second threshold value are values within the amplitude range of the input signal. The first threshold value is higher than the input signal in a case where the interface is an ineffective state. The second threshold value is lower than the input signal in a case where the interface is in the ineffective state. If the interface is in the ineffective state, therefore, the result of the judgment of the level of the input signal at the first threshold value and the result of the judgment of the level of the input signal at the second threshold value differ from each other. It is judged whether the interface is in an effective state or in the ineffective state depending on whether or not the results differ from each other.

Abstract: An operating system (GPOS) for universal device (GPU) for coupling a computer bus (PSB) to at least one specific link of a network (RN), the device includes a microprocessor (CPU) associated with at least one memory (SRAM) containing this system and means (MPC, B.sub.2, VRAM, B.sub.1, DMAC) for transferring frames from the computer bus to the link. The system is associated with a plurality of applications (A.sub.1 -A.sub.n) independent of one another, and includes a central core (NY) managing and organizing the work of each of the applications in real time, an applications manager (GA), which supervises and defines the state each of the applications must be in, and an intercommunications server (SA) for the applications, enabling each of them to request the services of another when that proves necessary. The core, the manager and the intercommunications server communicate between one another via system calls.

Abstract: A computer system having a removable hard disk drive is disclosed. The interposer card is modified to receive a docking bay which receives a cartridge which contains a hard disk drive. The docking bay includes the male portion of a zero insertion force connector and a first circuit board to which connects to the interposer card of the computer. The first circuit board also includes circuit paths between the male portion of the zero insertion force connector and the end which connects to the interposer card of the computer. The first circuit card also includes circuitry which allows "hot plugging" of the hard disk drive to the bus of the computer and which also acts as a lockout to prevent writing to the removable hard disk drive until after the computer system has been rebooted. The docking bay also includes a spring mechanism for ejecting the cartridge. A finger lever holds the cartridge in place and can be lifted to eject the cartridge.

Abstract: A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line.

Abstract: An arrangement for transmitting information from a first component of a computer system to a second component of the computer system including a source channel associated with the first component of the computer system; a destination channel associated with the second component of the computer system; apparatus for interconnecting the source and the destination channels; the source channel including apparatus for creating a stream of information in a prescribed format, apparatus for designating a destination channel as an address for the stream of information, and apparatus for transferring the stream of information to the apparatus for interconnecting the source and the destination channels; and the destination channel including apparatus for receiving a stream of information in the prescribed format from the apparatus for interconnecting the source and the destination channels, apparatus for receiving control signals apart from the stream of information, and apparatus for controlling the use of the stream o

Abstract: An I/O device includes a memory and a transmission reception control circuit addresses on the memory space are assigned to the memory. The transmission reception control circuit includes a plurality of registers to which addresses on the I/O space are assigned. The memory stores data to be transmitted to an external equipment or data received from the external equipment. The plurality of registers hold control data. The memory and the transmission reception control circuit are selectively activated in response to an identification signal. The transmission reception control circuit reads out data to be transmitted to the external equipment from the memory or writes data received from the external equipment into the memory in response to the control data held in the plurality of registers.

Abstract: In a data storage method for checksum DASD arrays, files are classified by length and/or other characteristic. Each relatively shorter file is written to an address or contiguous addresses typically on a single DASD of the array. The checksum stored on a checksum DASD is updated by reading the existing checksum, XORing that with the new data and writing the new checksum. Each relatively longer file is subdivided into portions all of the same size, and the number of equal portions is equal to the number of data DASDs where the file is to be written. The portions are interleaved in a stripe of addresses on the data DASDs, and the checksum of the portions is written to the checksum DASD. The characteristic transition length is dynamically varied in order that each interleaved file is provided with contiguous addresses matched to the file size.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.