Abstract: A control program for controlling an HDD and a rewrite program for rewriting the control program are stored together in a flash EEPROM. Upon entering the rewrite mode, a CPU in the HDD saves the control program in the flash EEPROM into the RAM. The CPU erases the flash EEPROM and restores the rewrite program of the RAM into the EEPROM. The CPU receives a new control program from a host computer and loads it in the flash EEPROM. The erasing of the flash EEPROM and the loading of the new control program are performed by the CPU in accordance with the rewrite program saved in the RAM.

Abstract: The system and method of the present invention provide a mechanism, for the purpose of efficiently interconnecting local area networks (LANs) across a frame relay network, by which LAN stations provide data flow control when the frame relay network becomes congested. The system of the invention comprises a Station Manager at the network end point internetworking unit (IWU) for managing the IWU, a LAN Manager for managing one or more LANs connected to the end point IWU, and Station Managers at each of the LAN stations managing the respective LAN station. In operation, the IWU receives from the frame relay network a congestion notification and the IWU Station Manager broadcasts this notification to its managed LAN station Station Managers. The LAN station Station Managers each examine the notification against its outstanding data to be transmitted and slows down data traffic that is destined for the congested portion of the frame relay network.

Abstract: The present invention discloses a message communication system and a distribution system. The feature of the present invention lies in various functions in the reception server, which is provided between the client server and the processing server. For example, the reception server performs reference processing, update processing, redundancy processing, etc. In the claimed invention, a reception server 20 is arranged between a client process 10, and a processing server 30. A demand discrimination stage 25 is provided for discriminating a demand only for a reference process and not requiring an update of medium and exclusive resources, and a demand for a reference process and reference and update process requiring a change of condition of the resource. The demand discrimination stage 25 classifies respective message communications systems into three aspects.

Abstract: A file input/output control device for a computer system of the present invention can, even in an environment where magnetic storage and semiconductor storage devices with quite different access speeds are concurrently used as the external storage, cancel exclusive control for film blocks without deteriorating the performance of higher speed storage. For this purpose, this device is provided with block write means to write the blocks in the buffer to the external storage block by block when a quiet point of the processing program is established and exclusion cancellation means to, each time the block write means terminates writing for a block, cancel exclusive control for that block.

Abstract: An apparatus and method for transferring data via DMA in data processing system from a host system to a transmission network. The transferred data is in longword format in which each longword consists of four bytes. Within a longword, valid bytes intended for transmission are contiguous. The adapter or I/O device includes a packet memory and a FIFO circuit interposed between the host system and packet memory to allow for differences in access speed of a host memory and the packet memory. The FIFO circuit contains four discrete FIFO circuits that are separately addressable for writing the bytes of each longword received from the host memory for storage in the FIFO circuit. The received longword is applied to a barrel shifter which aligns the first valid byte in the received longword with the one of the four discrete FIFO circuits containing a first available storage location at a current FIFO longword address.

Abstract: A multimedia information delivery network system is disclosed for delivering multimedia programs to a plurality of users at user-selected times. The network includes a wide area transmitter for transmitting the multimedia programs. Additionally, the network includes a plurality of network servers for receiving the programs and for selectively caching the programs for retransmission to downstream network servers and/or directly to one or more users at the user-selected transmission times. A scheduler receives the user-selected transmission times and, in response thereto, establishes a network server path by which the multimedia program is efficiently delivered to each user at the respective user-selected time.

Abstract: An apparatus which provides a high data transfer rate to and from an asynchronous bus. The apparatus includes a synchronous logic network to provide a transaction connection between the asynchronous bus and the data transfer device during an initial phase of the transaction when many determinations are required and an asynchronous logic network to provide data transfer between the asynchronous bus and the data transfer device during a subsequent phase of the transaction when very few determinations are required.

Abstract: An interface for connecting a local input device to a host, such as a telephone message receiving unit. The interface transfers data serially from the local input device to the telephone message receiving unit for print out or facsimile transmission thereby. Control of the interface is governed by a state machine having several states.

Abstract: A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.

Abstract: A multimedia information delivery network system is disclosed for delivering multimedia programs to a plurality of users at user-selected times. The network includes a wide area transmitter for transmitting the multimedia programs. Additionally, the network includes a plurality of network servers for receiving the programs and for selectively caching the programs for retransmission to downstream network servers and/or directly to one or more users at the user-selected transmission times. A scheduler receives the user-selected transmission times and, in response thereto, establishes a network server path by which the multimedia program is efficiently delivered to each user at the respective user-selected time.

Abstract: A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

Abstract: An information processing system is disclosed which includes an information processing apparatus having a plurality of slots on which a plurality of types of adapters can be mounted. Each type of the adapters has not its own address allocated by the system but will have, when mounted on any one of the slots, an address defined by the slot on which the adapter is actually mounted. In determining the system configuration, a processor accesses the addresses allocated to the slots sequentially and will receive adapter ID's from the adapters mounted on the slots.

Abstract: Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent. If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly.

Abstract: A computing system includes plural nodes that are connected by a communications network. Each node comprises a communications interface that enables an exchange of messages with other nodes. A ready queue is maintained in a node and includes plural message entries, each message entry indicating an output message control data structure. The node further includes memory for storing plural output message control data structures, each including one or more chained further monrtol data structures that define data comprising a message or a portion of a message that is to be dispatched. Control data structures that are chained from an output messsage control data structure exhibit a sequence dependincy. A processor is controlled by the ready queue and enables dispatch of portions of the message designated by an output message control data structure and associated further control structures.

Abstract: Shift-based control logic is used, in an exemplary embodiment, to implement in a microprocessor a circular prefetch queue that stores variable length instructions and transfers four instruction bytes at a time to an instruction decoder. The prefetch queue (10) includes a 16 byte sequential prefetch buffer (12). Access to the buffer is controlled by the shift-based control logic (14) which includes shifter logic that defines a four byte transfer window corresponding to an index byte together with the next three bytes in sequence. For each four-byte transfer operation, the shifter logic enables the four bytes within the transfer window to be read out for transfer to the instruction decoder (20). A transfer operation is initiated by the decoder, which presents the shift-based control logic with a bytes-used indicator, or shift increment. The shift increment denotes the number of bytes used by the previous four byte transfer via a four bit, one-hot selection.

Abstract: A method for managing Data Storage Medium (DSM) mount and demount decisions in an automated data storage library that dynamically optimizes both sequential and random data access workloads. The demount decisions adapt to time-varying characteristics in the relative workload mix. When the workload is primarily sequential, the mount and demount decision procedure favors longer mount residency for sequential access streams, reducing the robotic picker activity and reducing response time for mount requests. When the workload is predominantly random access, sequentially accessed DSM residency time is generally reduced and preemptive demounts are more readily implemented. The disclosed method provides for preemptive demounts and uses a two-element decision process to select either a Least Recently Used (LRU) or a Least Recently Mounted (LRM) decision parameter. The relative weights of the LRU and LRM decision tests are varied responsive to measured changes in data access workload characteristics.

Abstract: A partition establishment arrangement for use in a computer system comprising a plurality of processors interconnected by a communications network. The communications network comprises a plurality of communications nodes connected in a series of levels, with the nodes of at least some of the levels being controllable to connect to multiple ones of the nodes in a subsequent level. The partition establishment arrangement determines the controlling of the communication nodes to facilitate the partitioning of the processors into a plurality of partitions. The partition establishment arrangement, in a plurality of iterations, identifies conflict sets of processors to be assigned to respective partitions at a level, each conflict set identifying partitions for which, at a selected level, a processor may be connected to the same communications nodes in the next level.

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups can be prematurely ended on any 256 byte block boundary for several purposes, and all the frames of a given group must contain the same number of information field data words. Allowing frame groups to be ended on arbitrary block boundaries allows their transmission to start before all of the information field for the frame group has been received from a shared main processor storage. This capability of ending frame groups also allows high priority frame groups to interrupt the transmission of a relatively long data frame. Finally, the capability to end the frame group protects the information field of a stalled frame group since the CRC is sent and the idle sequence is resumed.

Abstract: A processing system 100 is provided which includes first and second hypernodes 101, each of the hypernodes 101 having at least first and second coherent interfaces 106. At least first and second interconnect network 107 are provided, the first network 107 coupling the first interfaces 106 of the first and second hypernodes 101 and the second interconnect network 107 coupling the second interfaces 106 of the first and second hypernodes 101.

Abstract: In a portable computer the BIOS software slows the system clock frequency during idle periods. The BIOS software returns the system to its normal operating frequency when an awaited event such as a keystroke occurs. In the event of an interrupt while the system clock is at the lower frequency, a hardware clock control circuit responds to the interrupt to promptly increase the system clock frequency to the normal value. By decoding the old frequency, new frequency and the several available frequencies, the change in frequency is timed to maintain proper phase and duty cycle without interruption.