Abstract: A data transfer system includes a buffer having a plural buffer areas for storing the data blocks transferred from plural central processors, and an external pointer storing an address data corresponding to an initial position of one of the buffer areas where a transferring data block is to be stored therein. The address data stored in the external pointer is renewed in accordance with a length of a data block to be transferred.

Abstract: A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and provides electrical communication to a number of peripheral devices. An asynchronous bus provides data communication between the first and second synchronous bus using handshaking signals so that the first and second clock signals operate independently of each other. The operating frequency and other parameters of the microprocessor and the first synchronous bus can be changed without requiring any changes to the second synchronous bus so that the microprocessor and the first synchronous bus can take advantage of advances in technology while allowing the second synchronous bus and the associated peripheral devices to remain compatible with previous versions of the computer system.

Abstract: A disk subsystem provided with a cache has a capability of executing writing of data of discontinuous dirty blocks on a cache memory into a disk and reading of data of discontinuous empty blocks on the cache memory through the effect of just one DMA transfer. When the dirty data discontinuously ranged on a cache segment is written on the disk, the microprocessor provides a bit-map to a harddisk controller (HDC) as control information for data transfer. If an i-th bit of the bit-map is "1", the HDC operates to write the i-th block data sent from a direct memory access controller (DMAC) onto the corresponding sector of the disk. If the i-th bit is "0", the microprocessor serves to stop the write of the data and control a read/write head to wait until it passes the corresponding sector.

Abstract: A highly secure, virus resistant, tamper resistant, object oriented, data processing system for depositing, withdrawing and communicating electronic data between one or more individual and/or networked computers comprising one or more computers for processing electronic data including one or more shared electronic storage devices for the temporary and/or permanent storage of said electronic data, each of said computers including custom configurable system programs for asynchronous depositing, withdrawing and communicating said electronic data to commonly shared electronic storage devices, and said programs permitting data archival, accountability, security, encryption and decryption, compression and decompression, and multi-processing capabilities.

Abstract: A data communication apparatus and associated method for switching from the Compatible mode to the ECM mode. The data communication apparatus receives a protocol message transmitted by a second data communication apparatus in accordance with a Compatible mode of operation. The first data communication apparatus then inverts the polarity of the received protocol message so that the inverted polarity protocol message is formatted in accordance with a G3 mode of operation. Then, the first data communication apparatus determines from the inverted polarity protocol message that the second data communication apparatus will receive the image data if it is transmitted in accordance with an ECM mode of operation. The image data is then transmitted in accordance with the ECM mode of operation to the second data communication apparatus.

Abstract: A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. Data rates can be adjusted by using "rate adjustment" time slots which can transmit data in some frames and "no data" in other frames. A particular time frame or template is provided which accommodates isochronous data, non-isochronous data, D channel data, maintenance data and frame synchronization signals. Non-isochronous operation and bandwidth allocation is independent and transparent to the isochronous data activity. Frame timing can be coordinated with one or more reference clock signals, e.g., from a public telephone or wide area network.

Abstract: A system for coupling sets of plurality of nodes that are memory coupled to pass write only data memory to memory via a data link that further includes an optical fiber controller coupled to each data link. Each controller is interconnected through fiber for high speed data transfers from one set of nodes to another. The controller is capable of connection implementing three and four cable interfaces. The data is transmitted through the fiber serially but the controller is adapted to receive parallel data and convert to serial form and vice versa.

Abstract: A method for compressing and subsequently decompressing digital data communicated in an interactive computer network, the network designed to provide informational and transactional services to a very large population of users. The method features steps for compressing bytes of network data before transmission by substituting variable-length code words obtained from a fixed, look-up table, and, reconstituting the bytes using a fixed, decompression look-up table when the code words are received at the data reception site.

Abstract: Method and apparatus for logging status information of a printer using an interactive network board coupled between the printer and a Local Area Network, includes the use of a Small Computer Systems Interface coupled to the board and having a data channel and a status channel, for transmitting print data to the printer over the data channel, transmitting printer status requests to the printer and receiving printer status data from the printer over the status channel. A memory is coupled to the board and is used for storing the received printer status data. A processor is also coupled to the board for adding beginning and end of print job indicia to the print data prior to transmission to the printer, and for causing the printer status requests to be transmitted to and received from the printer at a first predetermined interval (e.g. every minute). Furthermore, the processor calculates, at a second predetermined interval (e.g.

Abstract: Activity on a digital communication network is divided into periodic intervals and during a segment of each periodic interval a moderator station broadcasts a numerical count of the periodic intervals to all stations on the network. Each station has a memory in which a numerical value is stored, and a comparator that compares the numerical value to the numerical count received from the network. When the numerical count of the periodic intervals equals the numerical value, an apparatus within the station performs a defined operation, such as transmitting a message over the network or synchronizing a clock in the station to a master time standard. The equality of the periodic interval count and the numerical value also can be used to determine when to signal an external device. By using the count of the periodic intervals in this manner, the operation of several stations on the network can be coordinated.

Abstract: A managing apparatus of an image forming apparatus for communicating with a host computer at a remote place comprises: a communicating circuit to communicate with the host computer; a memory to store communication control data which is necessary to communicate with the host computer; and a controller for discriminating whether the communication control data has been stored in the memory or not when a setting command to instruct the setting of the communication control data from the host computer is received, for allowing the setting of the communication control data from the host computer when no communication control data is stored, and for inhibiting the setting of the communication control data from the host computer when the communication control data has been stored.

Abstract: A region of a communication buffer is divided into a control flag area where a communication mode flag and the like are set and a data area where communication data are set. In communication, a communication mode flag is set in the control flag area while communication data used in the specified communication mode are set in the data area. Thus, the data area can be shared among a plurality of communication modes. As a result, a capacity of the communication buffer can be reduced and the required communication period can be shortened.

Abstract: A master programmable controller is linked to one or more processing units by a network that enables communication to or from the units under system program control. The communication is based on data link instructions that are organized in blocks, as a series of a one or more data link instructions for corresponding units, and are accessed for execution in a sequence established by a sequence program, stored at the programmable controller. One or more of the data link instructions have a corresponding operation completion flag addressing instruction for specifying the address of a flag that is set where the respective operations of the data link instructions are complete. The efficient programming and execution of the sequence program is provided by assembling the data link instructions that define communications with one or more units into a group that is served by a single operation completion flag addressing instruction.

Abstract: A system and method for automatically identifying and configuring interface boards connected to a computer bus is disclosed. Each interface board contains a pair of interface ports that can be addressed by the system and a unique identification address. The interface boards are instructed to serially read the identification address and place a logic 10 in the two least significant bits of the data bus if the first data bit is a logic one. The serial read instruction is performed twice for each data bit in the identification address with a logic 01 data pattern placed on the data bus for the second serial read to assure that a floating data bus is not causing false readings. If no interface board responds to any particular read identification instruction, the system assigns a logic zero for that particular bit of the identification address.

Abstract: A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network.

Abstract: An invertor room air-conditioner for transmitting/receiving data between indoor and outdoor microprocessors, in which one microprocessor is synchronized with the remaining microprocessor using its internal clock pulse, while the microprocessors perform the data transmission/reception using dummy data previously stored therein, respectively, thereby removing the data transmission/reception errors and the influence of the exterior noises.

Abstract: A reverse address resolution protocol for use in a communication network which allows resolution logic to provide a higher level protocol information (such as an IP address) to a source of a request for such information, independent of the physical network address of such source. The protocol is used in a processor having a plurality of ports, at least one of such ports connected by a point-to-point channel to a remote network device. Reverse address resolution protocol is responsive to a resolution request from the remote network device across the point-to-point channel to supply the higher level protocol information based upon the port through which the resolution request is received, rather than the physical network address of the requesting device. Thus, a remote device may be coupled to a network, and connected to a central management site across a point-to-point communication link, in a "plug and play" mode.

Abstract: The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-part buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Abstract: A mechanism is provided for software configuration of ISA bus cards or other devices connected to a computer processor by a bus that does not provide for sharing of an address by multiple devices. Such a device is configured under software control by selecting multiple addresses commonly used by a read-only device, writing from the computer processor to the configuration logic at one of such addresses a predetermined data word as part of a predetermined security access sequence, writing from the computer processor to the configuration logic at one of the addresses configuration information including a device based address, and the configuration logic, in response to the predetermined security access sequence, storing the configuration information in configuration registers, thereby configuring the device. The addresses used may be addresses used by a game device, such as a joystick.

Abstract: An arrangement for selective filtering, e.g. one-way filtering, of messages received by a 2-port bridge from stations connected to two LANs of an extended LAN is provided. The bridge includes a message filtering database containing the addresses of all stations connected to one of the LANs. The database also contains a list of higher-level protocols employed by the stations. Associated with each protocol-type is information used by the bridge to dispose of the message. The message filtering database comprises a single table memory capable of supporting both ports of the bridge. The selective filtering process involves a two-step analysis by the bridge to determine whether to discard the message or forward it to another port. The analysis is based on a destination address and a protocol-type of the received message.