Abstract: In a computer system or process, sync point managers are distributed throughout each real machine for a plurality of execution environments, but all of the execution environments and sync point managers within one real machine share a common recovery facility and recovery log. A common recovery log is used by the recovery facility for all of the execution environments in the system. Different systems are interconnected by a communication facility and each has its own recovery facility and recovery log. A protected conversation can be initiated between the first and second execution environments in the same real machine, and the sync point managers within the respective execution environments coordinate the two-phase commit procedures associated with the protected conversations. A conversation manager within each real machine assists in routing the conversation between the first and second execution environments.

Abstract: A communication client is connected to multiple display servers. When a client of one of the display servers issues a communication, the communication client notes the communication in the display server coupled to the client and relays the communication to the other servers for use by clients of the other servers.

Abstract: Method and apparatus are disclosed for buffering data packets in a data communication controller. The communication controller is interfaced with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a packet number. Packet number assignment is carried out by a memory management unit within the communication controller which dynamically allocates to each assigned packet number one or more pages in a data packet buffer memory for the storage of the corresponding data packet. Upon issuing the assigned packet number, the physical addresses of the allocated pages of data packet buffer memory storage space are generated in a manner transparent to both the host processor and the control unit.

Abstract: A computer system, including at least one host (processor and operating system), a channel subsystem and at least one switch (together with an associated switch controller) for switchably connecting an I/O device (together with an associated I/O device control unit) to a host via said channel subsystem, in combination with means for dynamically managing I/O connectivity in said computer from each host. The I/O manager's functions are centralized at the host level across the computer system. Each host is responsible for an instance of the manager.

Abstract: When using a periodically interrupting timing device to implement software timers, a wide variety of resolutions for such timers can be provided with minimal interrupt overhead. This is achieved by dynamically reprogramming the frequency of the interrupting device to be at a selected low rate necessary to provide the resolution requested by the next, impending timer to expire. This is particularly useful when a periodic timing device is the only device available to implement variable timer resolutions.

Abstract: Access time is improved in a automated library system having sequentially stored data on a recording tape medium. A multiplicity of copies of the data is stored on different tape cartridges. The copies and the original are stored in different areas of the library. Each data segment stored on the tape media copy is stored in different areas of the media length from the original. The multiple copies are created and deleted independent of any user control. The usage of the original and any copies determine the number of copies and their residence times. The library manager selects the tape cartridge that can be retrieved in the shortest response time using the location of the original and the copies, the location on each cartridge of the data requested, the drive and library robot picker availability and the respective queues.

Abstract: A two-way data transfer device for the data interface between two data-exchanging cells including a data source and a data sink with at least one buffer provided in each cell. When the transmitter buffer is full or the receiver buffer is empty, a backward cell stop signal freezes the state of the data source or the data sink and the cell stop signals are controlled by status signals from the respective buffers.

Abstract: For controlling an original interruption request produced in each of peripheral units (12-1 to 12-N), the peripheral units are connected to an interruption control line (20) in common. When the original interruption request is produced, the peripheral unit in question continuously supplies an interruption control signal to the interruption control line unless the interruption control line is already supplied with the interruption control signal from other peripheral units. A timer circuit (23) of the peripheral unit in question times a preselected time interval from a time instant at which the peripheral unit in question begins to supply the interruption control signal to the interruption control line. The timer circuit suspends its operation while an interruption request line (10) is supplied with an interruption request signal from other peripheral units. When the time interval is timed, the peripheral unit in question continuously supplies the interruption request signal to the interruption request line.

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation.

Abstract: In a computer I/O system including a plurality of link-level facilities and a dynamic switch having a plurality of ports, each link-level facility being attached to an individual one of the ports, a mechanism and method for assigning a unique link level address to each of the link-level facilities. As each of the link-level facilities comes on line, it sends an acquire link address (ALA) frame and waits for a response (ACK) frame. The ALA frame may be addressed to a general to-whom-it-may-concern address and have a source address of who-am-I. Only a dynamic switch normally assigns link addresses. When receiving an ALA frame, the dynamic switch returns an ACK frame having a unique link address assigned to the sender of the ALA frame. Provision is made for determining if there is a dynamic switch present, or, if the link-level facilities are connected together by a static connection through the dynamic switch, for the link-level facility of a channel to assign the unique link addresses.

Abstract: In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit.

Abstract: A method for accelerating the writing of data to a Z buffer including the steps of reading the Z value presently stored at a position in the Z buffer; writing a new Z value to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote a new Z value to a position in the Z buffer, writing the Z value read back to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote the Z value read back to a position in the Z buffer, and comparing the Z value read from the position of the Z buffer with the new Z value; and rewriting the correct value to the Z buffer if the comparison of the Z value read from the position of the Z buffer with the new Z value demonstrates that the value written was incorrect.

Abstract: A programmable interrupt controller having a plurality of interrupt request inquest inputs and an interrupt request output for connection to a central processing unit (CPU) includes means for interrupting the CPU over the interrupt request output responsive to an interrupt request from any one of the interrupt request inputs and a priority resolver for assigning a priority position to each of the interrupt request inputs to create an interrupt priority hierarchy. The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

Abstract: An improved optical disk data storage system method are disclosed. In an optical disk storage system, a data compression device is interposed between a host computer and an optical disk controller to permit data storage and retrieval operations on an optical disk to occur at a faster rate than would otherwise be possible. Data is compressed when it is received by the optical disk controller and is decompressed before it is sent to the host computer. In this way data may be efficiently stored on an optical disk while providing plug compatibility with a host computer designed to store and retrieve data on a magnetic media data storage device.

Abstract: This invention is an improved method for transmit polling of buffered UARTs. For each polling interval, the method predicts the minimum number of characters needed to keep the transmitter from going idle before the next polling interval and places exactly that many characters in the transmit fifo.

Abstract: A data processor which comprises a pipeline processing mechanism for executing memory indirect addressing and register indirect addressing in an address calculation stage, checks whether or not an instruction writes an operand to a memory or register, makes each stage of the pipeline mechanism hold reservation information thereof in sequence, thereby reduces the frequency of stops of pipeline processing caused by processing of operand address calculation of the following instruction attending on a writing of the operand of the preceding instruction to a memory or register, so that data processing can be execute at a higher efficiency.

Abstract: Apparatus for monitoring and displaying the status of a local area network. The network includes a hub with ports for connection to various data terminal equipment in a star configuration and for connection to other hubs of the network. The hubs each have different types of plug-in modules which have ports for connecting the hub to different types of network cable such as fiber optic cable, unshielded twisted pair cable and shielded twisted pair cable. Information is automatically provided to a control console identifying the types of modules and the location of the modules in the hub so that an image of the actual hub can be displayed on the screen of the control console. The actual hub image shows the location and types of modules installed in the hub. In addition, information regarding the connection of each of the hubs to other hubs of the network is obtained and provided to the control console.

Abstract: The present invention describes an integer execution unit register file having one fewer write port by employing delayed writeback for data transfer instructions in a high speed processor. The integer execution unit comprises a register file with 32 separate registers, each 32-bits long. The register file is a write through register file. A four-stage instruction pipeline is employed to execute all integer instructions. The four stages are (1) Fetch, (2) Decode, (3) Execute, and (4) Writeback. For data transfer type of instructions such as, a load instruction, one extra instruction stage is usually required. The prior art processors add one extra write port to accommodate such data transfer type of instructions. The present invention delays the writing of the data transfer type instruction until the writeback stage of the next data transfer instruction. The result of the data transfer type instruction returns at the end of the writeback stage. The result is held in a temporary register.

Abstract: Apparatus and method for optimizing bus arbitration during direct memory access (DMA) data transfers across a nondedicated bus between a memory and/or a plurality of external devices each master having an arbitration priority. At least two nonoverlapping clocks are provided per transfer cycle and there is at least one transfer cycle per arbitration cycle. Arbitration priority requests are transmitted from each external device to an arbitration bus only at the rise of the first clock. At the end of the last clock, the priority code of the external device having the highest priority is determined to designate the external device which is to become bus master. Addresses and data are transferred between the designated bus master and the memory or another of the external devices via the nondedicated bus during the next cycle after a then active bus master relinquishes control. The priorities of the external devices can be changed dynamically.