Abstract: Method for realizing a binary counter that changes a partly permuted data word stored in a non-volatile memory and including a counter and a working memory and storing a data word in the form of memory words in the non-volatile memory. The method further comprises reading the memory words of the data word and storing the memory words in the working memory while performing an inverse reordering of k permutation bits of the data word, applying an inverse bijective mapping function to the k permutation bits of the data word, altering the data word, applying a bijective mapping function to the k permutation bits of the data word, performing a reordering of the k permutation bits, and checking each memory word for deviations from the memory word stored in the non-volatile memory and storing only those memory words in the non-volatile memory again for which this is the case.

Abstract: Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

Abstract: Folding noises into signal bands are reduced and steeper cutoff characteristics are achieved without any increase in the scale of the circuit of a decimation filter attributable to the order of the filter coefficients and the bit precision of the same. Smaller attenuations are achieved in regions that do not contribute to folding noises, and filter coefficients are used to primarily attenuate signal components in regions contributing to folding noises and having a certain band width located about frequencies that are integral multiples of a decimated sampling frequency of 8 fs, thereby reducing folding noises compared to the prior art. Attenuations smaller than those in the prior art are achieved in other regions that do not contribute to folding noises to allow the filter coefficients to be used to make cutoff characteristics steeper accordingly, thereby achieving steeper cutoff characteristics while keeping folding noises at the level of the prior art.

Abstract: The present invention provides an adaptive filter. In one embodiment, the adaptive filter includes a solution vector generator that develops a sparse expression of an initial solution vector. In addition, the adaptive filter includes a proportionate normalized least mean squares (PNLMS) analyzer, coupled to the solution vector generator, that employs the sparse expression to converge upon at least one coefficient for the adaptive filter.

Abstract: The present invention relates to a distributed arithmetic module employing a zero input detection circuit that reduces electric power consumption by avoiding unnecessary calculation. An apparatus for performing a discrete cosine transform (DCT) on a video signal, including; input unit for receiving the video signal in a block by block basis; discrete cosine transform (DCT) unit for receiving each image data block from the input unit and conducting a discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) operation on the received image data block to generate a transformed image data block containing N×M pixel value; zero input detect unit for determining whether pixel values of a current image data block are all “0” and generating a detection signal in order to bypass the DCT/IDCT performing on the current image block; and output unit for outputting the transformed image data block as a transformed video signal.

Abstract: For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method. In one embodiment, the circuit includes: (1) left-shift circuitry for aligning a fractional part of the floating-point result with a most significant bit of the datapath and irrespective of a width of the fractional part to yield a shifted fractional part and (2) rounding circuitry, coupled to the shift circuitry, that rounds the shifted fractional part.

Abstract: A random number data generator includes a plurality of oscillation units and an AND circuit for outputting random number data produced in at least one oscillation unit when each of the entire oscillation units has oscillated a predetermined number of times, wherein high-reliability random number data can be generated efficiently.

Abstract: A method for implementing a multiplier-less FIR filter is disclosed, in which the FIR filter performs the convolution of H ? ( z ) = ? k = 0 N - 1 ? ? h k ? z - k , where hk is the k-th coefficient of the FIR filter. The dynamic range of the filter coefficients is compressed by a transformation: H ? ? ( z ) = H ? ( z ) ? ? i = 1 m - 1 ? ? ( 1 + ? i ? z - ? ) m ? i = 1 m - 1 ? ? ( 1 + ? i ? z - ? ) m , where parameters ? and ? are chosen depending on filter type, ?1??i?1, and m denotes iteration numbers of coefficient operation of transformation, so as to avoid the serious quantization error caused by the phenomenon of SPT distribution. Then, the compressed coefficients are quantized into SPT numbers, and the coefficients are optimized by removing redundant STP numbers.

Abstract: The invention relates, in general, to circuits and techniques for generating numbers and, in particular, to digital semiconductor circuit for generating large numbers. For generating such large numbers a large number generator circuit is used, comprising first means having an output for providing a first operand to a first input of a processing unit, second means having an output for providing a second operand to a second input of said processing unit, an output of said processing unit being operatively connected to an input of an arithmetic unit for generating a large number, wherein said second operand is generated by said second means using a parameter having far fewer number of p bits than the number of bits of the first operand. The use of parameters of a significant shorter length of bits has been proven to be less time consuming and much faster in generating large numbers, as special operands of a significant long length of bits are no longer to be read and written from and to the memory unit.

Abstract: Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second adder for adding a portion of bits of the first output, the second adder being operable to add a plurality of m-bit addends, m being smaller than or equal to n. The apparatus further comprising at least two electronic-circuits, operatively associated with the first adder and the second adder. The first adder, the second adder and the at least two electronic-circuits are constructed and designed to obtain the value, the overflow status and a sign of the addition of the at least three data inputs, using predetermined parity rules being associated with a parity characteristic of the at least three data inputs.

Abstract: A method and a device are described for filtering a variable. A first filtering arrangement is used for forming an output variable as a function of an input variable, the first filtering arrangement having at least a delaying effect. The input variable of the first filtering arrangement is corrected using a correcting variable which is obtained by starting from the input variable of the first filtering arrangement and by filtering, using a second filtering arrangement.

Abstract: According to the invention, optimization of an application by elimination of redundant operand conversions is disclosed. According to one embodiment, the optimization comprises receiving an application that includes one or more operations, with one or more operands of the operations being converted from a first format to a second format before performing an operation; determining the origin of the one or more operands that are converted from the first format to the second format; and if the origin of any of the one or more operands that are converted from the first format to a second format is a conversion from the second format to the first format, then eliminating the redundant conversion from the second format to the first format and from the first format to the second format.

Abstract: Disclosed is a frequency converter with an excellent frequency characteristic, having a minimized number of multipliers. A digital down-converter includes a decimator/mixer, an interpolator and a channel filter. The decimator/mixer performs quadrature conversion from a real signal to complex signals, frequency conversion by a frequency K?, and 1/(M×I)-fold decimation on a signal obtained by sampling an RF/IF signal S(i) by an A/D converter. The interpolator is comprised of I-fold up-samplers and lowpass filters, and performs I-fold interpolation on the outputs from the decimator/mixer. The channel filter is comprised of lowpass filters having a band characteristic given to a communication channel, and outputs band-rejected baseband signals i(j) and q(j) by filtering the outputs of the interpolator.

Abstract: A random number generating system operates to generate an output number bit sequence based on an entropy estimation of a true random number bit sequence, the randomness of the output number bit being an improvement of the randomness of the true random number bit sequence. A physical random number generator communicates the true random number bit sequence to an entropy estimator, which generates an estimation signal indicative of the randomness of the true random number bit sequence. The estimation signal is communicated to a decimator whereby, in accordance with estimation signal, the decimator generates the output number bit as a representation of a decimation of a mixing of the true random number bit sequence and the pseudo random number bit sequence, or as a representation of a decimation of the pseudo random number bit sequence when the pseudo random number bit sequence is generated as a function of the true random number bit sequence.

Abstract: A CORDIC method and a CORDIC architecture applied in vector rotation are disclosed. An elementary angles set is extended by representing the elementary angles as the arctangent of the sum of two single signed-power-of-two terms to an extended elementary angles set. A combination of elementary angles is found from the extended elementary angles set such that the residue angle error can be minimized. A quantized scaling factor is used to scale the combination of elementary angles after being micro-rotated.

Abstract: A system and method for calculating an output value from a plurality of input sample values contributing to the output value in accordance with a respective weight value. A first intermediate value is interpolated for a first offset value from a first plurality of the input sample values and a second intermediate value is interpolated for a second offset value from a second plurality of the input sample values. The offset values are representative of the weight values of the input samples of the respective plurality of the input samples. The first and second intermediate values are combined to produce a resultant value which is subsequently blended with the remaining input sample values of the plurality in accordance with respective scaling values assigned to the resultant value and the remaining input sample values.

Abstract: In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.

Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.

Abstract: The present invention generally relates to provide a clock balanced segmentation digital filter, which is provided with an optimum area of a data path. The digital filter includes a controlling unit, which is connecting with a register, a multiplexer unit, and an arithmetic and logic unit. The present invention utilizes the controlling unit to initialize the filter parameter stored in the register and to segment the whole logic operation procedure to a plurality of operation steps and to arrange the operation procedure. The multiplexer unit is connecting with the register and the arithmetic and logic unit. The multiplexer unit controlled by the controlling unit is choosing the require parameter and data to output into the arithmetic and logic unit to perform the operation. The operation result is stored in the register for using as the following operation parameter. The present is provided with advantages of scaling down the area of logic circuit, low power consumption and rapid operation.

Abstract: A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.