Patents Examined by D. M. Collins
  • Patent number: 6544819
    Abstract: A method and an apparatus wherein the thin semiconductor wafer is cut into a unit of a thin semiconductor element under the condition of being stuck on an adhesive sheet. A group of the semiconductor elements are removed from the adhesive sheet at high speed without incurring and breaking each semiconductor element thereof, and the semiconductor elements are picked up from the removed group of the semiconductor elements by a predetermined unit.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Odajima, Kazuyuki Futagi, Makoto Matsuoka
  • Patent number: 6489199
    Abstract: A two-step formation process provides conformal coverage at both the bottom surface and one or more side walls of an opening for various applications, e.g., high aspect ratio contact liners or storage cell capacitor electrode applications, and provides conformal coverage on any features requiring such coverage. A method for forming a conformal layer in the fabrication of integrated circuits includes providing a substrate assembly including at least a generally horizontal first surface and a second surface extending therefrom. A first portion of the layer is formed selectively on the horizontal first surface during a first period of time and a second portion of the layer is deposited selectively on the second surface during a second period of time.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: December 3, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Weimin Li, Gurtej S. Sandhu
  • Patent number: 6489180
    Abstract: A flip-chip packaging process is proposed, which can help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads without being made open-circuited by the electrically-insulative material being used for flip chip underfill. The proposed flip-chip packaging process is of the type utilizing a no-flow underfill technique to prevent short-circuiting between neighboring solder bumps, and is characterized in the fabrication of electrically-conductive sharp-pointed studs over substrate-side bond pads to prevent open-circuiting between chip-side solder bumps and substrate-side bond pads.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: December 3, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying Chou Tsai, Shih Kuang Chiu
  • Patent number: 6479350
    Abstract: CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: November 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zicheng Gary Ling, Todd Lukanc, Raymond T. Lee
  • Patent number: 6472756
    Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: October 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Gurtej Singh Sandhu, Kirk Prall, Sujit Sharan
  • Patent number: 6455380
    Abstract: A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: September 24, 2002
    Assignee: LG Semicon Co., Ltd
    Inventor: Gyu Han Yoon
  • Patent number: 6440791
    Abstract: A self-aligned bit-line contact opening and node contact opening fabrication process having the following features: Etching of the periphery MOS spacer is performed before ion implantation of the periphery MOS source/drain region, using the same photoresist layer as a mask. A self-aligned bit-line (node) contact opening and a periphery gate contact opening, above the periphery MOS gate, are formed simultaneously. The etching of the memory cell MOS spacer is performed after the self-aligned bit-line (node) contact opening has been formed. At the same time, the cap layer above the periphery MOS gate, exposed by the periphery gate contact opening, is etched through.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: August 27, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Patent number: 6440786
    Abstract: The present invention relates to the fabrication of a boron carbide/boron semiconductor devices. The results suggest that with respect to the approximately 2 eV band gap pure boron material, 0.9 eV band gap boron carbide (B5C) acts as a p-type material. Both boron and boron carbide (B5C) thin films were fabricated from single source borane cage molecules using plasma enhanced chemical vapor deposition (PECVD). Epitaxial growth does not appear to be a requirement. We have doped boron carbide grown by plasma enhanced chemical vapor deposition. The source gas close-1,2-dicarbadecaborane (orthocarborane) was used to grow the boron carbide while nickelocene (Ni(C5H5)2) was used to introduce nickel into the growing film. The doping of nickel transformed a B5C material p-type relative to lightly doped n-type silicon to an n-type material. Both p-n heterojunction diodes and n-p heterojunction diodes with n- and p-type Si [1,1,1] respectively.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: August 27, 2002
    Assignee: Board of Regents, University of Nebraska-Lincoln
    Inventor: Peter A. Dowben
  • Patent number: 6432728
    Abstract: A new method is provided for determining the optimum film thickness of a film that is to be deposited over a semiconductor surface. The invention observes the electrical current and the therefrom resulting torque that is supplied to a rotating part of a polishing apparatus, from this the CMP end-point can be determined for a reference film that has been deposited. This technique is known as the “CMP end-point detection” technique. The invention addresses observing CMP end-point curves for films of various thicknesses and compares these CMP end-point curves of one film thickness with each other and calculates a deviation for multiple layers (deposited on different wafers) of that film thickness. The process is repeated for different film thickness. The film thickness that has a deviation of the CMP end-point curve that closest resembles an optimum deviation is the film thickness that is selected as having the optimum thickness for the deposition of that film.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: August 13, 2002
    Assignee: ProMOS Technologies, Inc.
    Inventors: Shuo-Yen Tai, Ming-Cheng Yang, Jiun-Fang Wang, Champion Yi
  • Patent number: 6429517
    Abstract: A semiconductor device is provided which improves reliability by preventing connection defects with extensions and interface peeling occurring between a substrate and a sealing resin, and which can reduce the production cost by simplifying a fabrication process. In this semiconductor device, each lead 16 for electrically connecting an electrode terminal 12 of a semiconductor chip to an external connection terminal 14 comprises an extension 17 extending parallel to an electrode terminal formation surface of the semiconductor chip 10 with a predetermined distance from the electrode terminal formation surface, an external connection terminal post 22 provided to one of the end portions of the extension 17, and an electrode terminal post 24 connected to the electrode terminal 12 of the semiconductor chip 10. The electrode terminal post 22 and the extension 17 are sealed by a sealing resin 18, and the distal end portion of the external connection terminal post 24 is exposed from the sealing resin 18.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: August 6, 2002
    Assignee: Shinko Electric Industries Co., LTD
    Inventors: Mohan Kirloskar, Michio Horiuchi, Yukiharu Takeuchi
  • Patent number: 6417018
    Abstract: The present invention relates to a method of encapsulating a plurality of chip and board pre-assemblies. Each pre-assembly has first and second surfaces. The method includes positioning a first mold half in a sealing relationship with each first surface of the pre-assemblies and positioning a second mold half adjacent each second surface of the pre-assemblies. The first mold half is filled first thereby forcing each second surface of the pre-assemblies into a sealing engagement with the second mold half. The second molding section is then filled, to result in an asymmetrically overmolded chip and board assembly.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: July 9, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Mark S. Johnson
  • Patent number: 6414390
    Abstract: A semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument are such that without substrate material selection or additional steps after connection, connection reliability can be assured, while direct connection to a substrate is possible, further allowing an electronic instrument to be made more compact and lightweight. The semiconductor device comprises a semiconductor chip (100) having electrodes (104), an interconnect layer (120) connected to the electrodes (104), a conducting layer (122) provided on the interconnect layer (120) avoiding the area of the electrodes (104), an underlying metal flyer (124) having a size larger than the peripheral outline of the conducting layer (122) provided on the conducting layer (122) and easier to be deformed than the conducting layer (122), bumps (200) provided on the underlying metal layer (124), and a resin layer (126) provided on the periphery of the conducting layer (122).
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: July 2, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Kazuhiko Nozawa
  • Patent number: 6410414
    Abstract: A method for fabricating a semiconductor device reduces soft errors, thereby enhancing reliability of the semiconductor device. In the method, a benzo cyclo butene (BCB) layer having a low water intake rate and an excellent blocking effect against alpha particles is formed between an alpha particle source such as a solder ball and sensitive integrated circuit devices such as a memory cell.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: June 25, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-hern Lee
  • Patent number: 6395580
    Abstract: A method for conducting a backside failure analysis on a ball grid array (BGA) package that does not require a chemical etching step is described. In the method, a substrate can first be removed mechanically from the BGA package to expose a plastic encapsulated IC chip. The molding compound on the backside of the IC chip can then be removed by a mechanical method such as polishing or preferably, chemical mechanical polishing. Simultaneously with the exposure of the backside of the IC chip, the ends of a plurality of bonding wires which are connected to the bond pads on the top surface of the IC chip is also exposed. A plurality of probe needles or a bonder can then be used to make electrical contact with the ends of the bonding wires such that signals may be fed into the IC chip for conducting a failure analysis.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: May 28, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Fouriers Tseng
  • Patent number: 6391798
    Abstract: A process for forming a semiconductor wafer with a flat surface is disclosed. In the process, a bare semiconductor wafer that has been sawed from an ingot is provided. A layer of planarization material is formed on at least one major surface of the semiconductor wafer. The layer of planarization material is placed into contact with a respective object having a flat surface. Pressure is applied to cause the planarization material to flow and impart a planar, surface to the layer of planarization material. The planarization material is then hardened. The flat surface is separated from contact with the respective layer of hardened material. The surface flatness is then transferred into the underlying substrate surface.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: May 21, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Richard Alden DeFelice, Judith Prybyla
  • Patent number: 6380059
    Abstract: A method is proposed for use to break integrally-connected electrically-conductive traces on a circuited substrate used in TFBGA (Thin & Fine Ball Grid Array) semiconductor packaging technology, so as to make the electrically-conductive traces open-circuited for the implementation of open-circuited testing on the electrically-conductive traces on the substrate. The proposed method is characterized in the forming of a resistively-enlarged point at the terminal of each electrically-conductive trace on the substrate, which can be melted away while leaving each electrically-conductive trace intact simply by applying an electrical current of an adequate magnitude to pass through each electrically-conductive trace. As each electrically-conductive trace is open-circuited, an open-circuited testing procedure can be then performed on the electrically-conductive on the substrate.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: April 30, 2002
    Inventors: Tzong-Da Ho, Chien-Ping Huang, Chiao-Yi Lee
  • Patent number: 6376280
    Abstract: A microcap wafer-level package is provided in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer has gaskets formed thereon using a thick photoresist semiconductor photolithographic process. Bonding pad gaskets match the perimeters of the bonding pads and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer. The cap wafer is then placed over the base wafer to cold weld bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket. The cap wafer is then thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for connecting wires from a micro device utilizing system.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: April 23, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Richard C. Ruby, Tracy E. Bell, Frank S. Geefay, Yogesh M. Desai
  • Patent number: 6376277
    Abstract: A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical connections which extend from bond pads on the semiconductor die to corresponding bond pads on the substrate. An encapsulant is formed over each segment and contains grooves which correspond to the grooves of the substrate. Break points are thus formed at the grooves to permit the segments to be easily detached from the substrate to form individual integrated circuits.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6376341
    Abstract: A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a masking layer overlying the ONO layer, patterning the masking layer into a resist mask, implanting the semiconductor substrate with a p-type dopant to create a p-type region, and laterally diffusing the p-type region. In one preferred embodiment, the lateral diffusing of the p-type region includes exposing the semiconductor substrate to a thermal cycle. Preferably, the thermal cycle is a rapid thermal anneal or a furnace anneal.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George J. Kluth, Arvind Halliyal
  • Patent number: 6372543
    Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: April 16, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony Chiu, Tom Quoc Lao, Harry Michael Siegel, Michael J. Hundt