Abstract: In a method of forming a polycrystalline silicon film, the polycrystalline silicon film is formed under film formation conditions of a film formation rate of 0.9rav to 1.1rav, where rav (nm/minute) is an average rate of forming the polycrystalline silicon film on each of a plurality of substrates on which oxide films are formed so as to provide the roughness of the interface between the oxide film on the substrate and the polycrystalline silicon film of less than 1 nm. As a result, it is possible to decrease the roughness of the interface between a gate oxide film and the polycrystalline silicon film and to improve reliability for ensuring the long-time use of the gate oxide film.

Abstract: For providing a method and an apparatus thereof, wherein a thin semiconductor wafer is cut out into a unit of a thin semiconductor element under the condition of being stuck on an adhesive sheet, a group of the semiconductor elements are removed from the adhesive sheet at high speed without injuring and breaking each semiconductor element thereof, and the semiconductor elements are picked up from the removed group of the semiconductor elements by a predetermined unit, according to the present invention, the separating method comprising: a separation step for holding on a chuck a group of semiconductor elements with positioning objects, being stuck on an adhesive sheet fixed on a frame at periphery thereof under condition of a semiconductor wafer and cut into a unit of a semiconductor element, for cutting the adhesive sheet around the group of semiconductor elements being held, and for striping the cut adhesive sheet from said group of semiconductor elements being held; and a storing step for storing into a tr

Abstract: A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.

Abstract: A method is proposed for forming a constricted-mouth dimple structure on a lead-frame die pad for an integrated circuit (IC) package. This method can help secure the molded compound of the integrated circuit package more firmly in position to the die pad so that the molded compound would be less likely subjected to delamination. This method is charaterized in the use of a stamping process to punch on a selected part of the die pad that is located around the mouth of an originally-formed inwardly-tapered dimple structure, thereby narrowing the mouth of the inwardly-tapered dimple structure, resulting in the forming of the intended constricted-mouth dimple structure. Since this method requires only an additional stamping process to narrow the originally-formed inwardly-tapered dimple structure, it is much easier and more cost-effective to implement than the prior art.

Abstract: The present invention relates to a method and system of encapsulating a plurality of chip and board pre-assemblies. Each pre-assembly has first and second surfaces. The method includes positioning a first mold half in a sealing relationship with each first surface of the pre-assemblies and positioning a second mold half adjacent each second surface of the pre-assemblies. The first mold half is filled first thereby forceing each second surface of the pre-assemblies into a sealing engagement with the second mold half. The second molding section is then filled, to result in an asymmetrically overmolded chip and board assembly.

Abstract: Microelectronic packages may be fabricated by forming a release layer on a process substrate. A thin film decal is formed on the release layer. The thin film decal includes first and second opposing decal faces, first decal input/output pads on the first decal face, second decal input/output pads on the second decal face and at least one internal wiring layer that electrically connects at least one of the first and second decal input/output pads. The first decal input/output pads are adjacent the release layer and the second decal input/output pads are remote from the release layer. A dielectric adhesive layer is then formed on the second decal face. The dielectric adhesive layer includes first and second opposing dielectric layer faces and conductive vias therein that extend between the first and second opposing dielectric adhesive layer faces.

Abstract: A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.

Abstract: A new method is provided for the creation of layers of dielectric that are used for metal stack interconnect layers where the metal stack exceeds five layers. A stack of five layers of metal interconnect lines contains one layer of Intra Metal dielectric (ILD) and four layers of Inter Metal dielectric (IMD). One or more of the layers of IMD can be formed in the conventional method. One or more of the layers of IMD can be formed in the conventional method after which a layer of high compressive PECVD is deposited over this one or more layers of IMD. The layer of high compressive PECVD provides a crack resistant film that eliminates the formation of cracks in the surface of the IMD.

Abstract: A method of making a semiconductor chip package utilizes a film carrier to support a semiconductor chip. The method comprises the steps of: forming a plurality of through-holes in a film carrier; laminating a metal layer on the film carrier; etching the metal layer to form a die pad and a plurality of connection pads disposed corresponding to the through-holes; forming a metal coating on the surfaces of the die pad and the connection pads which are not covered by the film carrier; attaching a semiconductor chip to the die pad; electrically coupling the semiconductor chip to the connection pads; forming a package body over the film carrier and the semiconductor chip; and removing the film carrier.

Abstract: A method of manufacturing a semiconductor device is provided in which a semiconductor substrate with a dielectric layer has channel and via openings formed in the dielectric layer. A seed layer is formed over the dielectric layer and in the openings followed by a resist over the seed layer. The resist is then removed outside the openings. The seed layer outside the openings, which is not covered by the resist, is removed and the seed layer in the openings remains intact because of the resist in the openings. The resist inside the openings is removed and the seed layer inside the openings is electroless plated to fill the openings and form the channels and vias for interconnecting the semiconductor device.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: The present invention is related to a method for manufacturing lead frames and a lead frame material including an intermediate layer and a top layer. The intermediate layer is composed of a layer of nickel-cobalt alloy having 5 to 30 wt. % of cobalt and a thickness of 3 to 20 microinches and a layer of nickel or nickel alloy having a thickness of 10 to 80 microinches. The intermediate layer can inhibit the diffusion of the base metal to the surface of the leads. The top layer consisting of gold or gold alloy, which is composed of gold and at least one metal selected from the group consisting of palladium, silver, tin and copper and has at least 60 weight percent gold, has a thickness of 0.1 to 5 microinches.

Abstract: A power semiconductor device having an improved high breakdown voltage and improved productivity, and a fabrication method thereof are provided. The power semiconductor includes a collector region of a first conductivity type formed in a semiconductor substrate, a base region of second conductivity type formed in the collector region, and an emitter region of the first conductivity type formed in the base region. A channel stop region is formed being spaced a predetermined distance from the base region. An insulative film, a semi-insulating polycrystalline silicon (SIPOS) film, and a nitride film patterned respectively to expose the emitter region, the base region, and the channel stop region are sequentially deposited on the semiconductor substrate. A base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region are formed.

Abstract: Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract: A chip package according to an embodiment of the present invention includes an integrated chip having a plurality of chip pads formed thereon, and a passivation film formed in such a manner that the chip pads are exposed. A plurality of metal wirings are connected to the chip pads on the upper surface of the passivation film, and externals balls electrically connected to the metal wirings. A molding resin layer is formed on the upper portion of the semiconductor chip such that the upper surfaces of the external balls protrude therefrom.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium bitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Abstract: The method of the present invention is related to the fabrication of a copper-based multilevel interconnect structure. This copper-based multilevel interconnect structure is based on the formation of vertical metal connections through copper-containing metal stud growth on an underlying horizontal metal pattern, followed by a stud encapsulation step against copper diffusion into the surrounding dielectric, i.e. the insulating layers. This method is of particular interest when the insulating layers used to obtain this interconnect structure are polymer layers with a low dielectric constant and preferably with a high degree of planarization.

Abstract: Protective tape is bonded onto a rear surface of a semiconductor element prior to a resin sealing step, and then only a primary surface of the semiconductor element is sealed with a resin layer. Cracks and warping which would otherwise be caused by an external force or foreign matter at an exposed rear surface of the semiconductor element are prevented. This facilitates a surface polishing step and also results in a lower profile for the semiconductor device, because the rear surface is not sealed with resin.

Abstract: Laser apparatus and methods are provided for synthesizing areas of ceramic substrates or thin films, such ceramics as Silicon Carbide and Aluminum Nitride, to produce electronic devices and circuits such as sensors as integral electro circuit components thereof. Circuit components such as conductive tabs, interconnects, wiring patterns, resistors, capacitors, insulating layers and semiconductors synthesized on the surfaces and within the body of such ceramics. Selected groupings and arrangements of these electronic circuit components within the substrates or thin films provide a wide range of circuits for applications such as digital logic elements and circuits, transistors, sensors for measurements and monitoring effects of chemical and/or physical reactions and interactions of materials, gases, devices or circuits that may utilize sensors.