Abstract: The invention is an assembly and method for bonding an optical component to a base member. The component is mounted to a block which includes a centerline extending between two opposing surfaces. A pair of stop members are included on the surface of the base member, and these members serve to pin the centerline during heating and cooling of the assembly so that the position of the component is controlled.

Abstract: An angle cavity resonant photodetector assembly (8), which uses multiple reflections of light within a photodetector (14) to convert input light into an electrical signal. The photodetector (14) has a combination of generally planar semiconductor layers including semiconductor active layers (20) where light is converted into an electrical output. The photodetector (14) is positioned relative to a waveguide (10), where the waveguide (10) has a waveguide active layer (22) located between a pair of waveguide cladding layers (24) and (26) and includes a first end (28) for receiving light and a second end (30) for transmitting the light to the photodetector (14). The photodetector (14) has a first reflector (12) and second reflector (16) that provides for multiple reflections across the semiconductor active layers (20).

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: In the known method, a semiconductor element (1) is provided with two connecting conductors (2, 3) by arranging, preferably a large number of elements (1) between first and a second conductive plate (5, 6), the two connecting conductors (2, 3) secured at the upper surface and lower surface of an element (1) being formed from the two plates (5, 6). The first connecting conductor (5) is formed from a part (2) of the first plate (5) which borders on an opening (7), and the element (1) is covered with a protective envelope (4). The known method has the drawback that the devices obtained are not always directly suitable for surface mounting. Furthermore, the reliability of the device is sub-optimal.

Abstract: A technique for reducing burrs formed by a die set having a cutting insert with a screw clearance, fastened to a holding plate by a mounting screw. In one embodiment, a clamping plate is fabricated with a shape defined by two intersecting circular arcs having different diameters, a smaller arc matched to the screw clearance in the cutting insert, and a larger arc matched to an arc defined in the pocket of the holding plate. The holding plate also has a threaded hole centered in the holding plate arc. The clamping plate is fastened to the holding plate with the smaller arc abutting the screw clearance in the cutting insert, and the larger arc abutting the holding plate arc. The clamping plate reduces lateral motion of the cutting insert within the mounting plate, when the mounting screw is tightened.

Abstract: A semiconductor chip packaging assembly comprising a frame having a central aperture, a flexible substrate attached to the frame across the central aperture, and a unitary support structure having a plurality of apertures therethrough attached to the substrate within the central aperture of the frame with at least some of the substrate terminals underlying the unitary support structure. A chip is disposed within each aperture and attached to the substrate with the electrical contacts of the chip connected to the substrate terminals. A compliant layer is disposed between the substrate and the unitary support structure and between the substrate and the chip.

Abstract: A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

Abstract: A semiconductor light emitting device having a plurality of semiconductor light emitting elements of different emission wavelengths capable of reducing the number of parts and simplifying the configuration of an optical system, comprising a substrate and at least two stacks each comprised of an epitaxial growth layer comprised of at least a first conductivity type clad layer, an active layer, and a second conductivity type clad layer on the substrate, the stacks being spatially separated, the compositions of at least the active layers being different between the stacks, and a plurality of types of light having mutually different wavelengths being emitted from the active layers in parallel with the substrate and in substantially the same direction, and a method for producing the same.

Abstract: A method for forming a semiconductor device includes forming a conductive bump on one or more of bond pads of a semiconductor substrate of a semiconductor wafer. A top or uppermost portion of each conductive bump is then planarized. The exposed portions of an active surface of the semiconductor wafer are filled with a layer of encapsulation material. The conductive bumps are reformed to their preplanarized shape and the semiconductor wafer is then diced to form singulated semiconductor dice. A preferred method of the invention also includes placing each singulated die in a mold to complete a second encapsulation step wherein a layer of encapsulation material is formed on the back surface or, alternatively, on the back and side surfaces of the semiconductor die in order to encapsulate the back, or the back and sides, of the semiconductor die.

Abstract: A semiconductor device with advanced functions and an improved factor of effective mounting area comprises a semiconductor chip on which an IC or the like is formed; a plurality of external connector electrodes having a block form which are connected with a plurality of electrodes of the semiconductor chip, arranged near the circumference of the semiconductor chip at a prescribed distance from the semiconductor chip, and composed of a substrate other than the semiconductor chip; a wiring substrate which is arranged face to face with the semiconductor chip and the external connector electrodes, and a wiring pattern for electrically connecting each electrode of the semiconductor chip with the external connector electrodes is formed on the surface. Connectors connect the wiring pattern with both electrodes of the semiconductor chip and external connector electrodes and form a prescribed space between the wiring substrate and the semiconductor chip. A method of manufacturing such devices is also disclosed.

Abstract: Methods of fabricating an interconnection to an underlying microelectronic layer include removing a portion of the insulation layer to form a plurality of contact holes having different contact sizes therethrough and thereby expose a portion of the microelectronic layer. A conductive material is deposited on the insulation layer and in the contact hole with a sufficient thickness such that a bridge is generated in the largest contact hole. The deposited conductive material is then reflowed to fill the contact hole and form an interconnection to the underlying microelectronic layer, by supplying a high pressure such that at least the void formed in the largest contact hole is filled. The conductive material may be planarized to thereby expose the insulation layer. The present invention may be applied to an asymmetrical contact hole, for example, a dual damascene structure.

Abstract: A method for making a semiconductor package firstly provides a lead frame having a first surface and a corresponding second surface. The lead frame includes at least a package unit that further includes a die pad, and a plurality of leads disposed on the periphery of the die pad where each of the leads further includes a neck portion. The method then attaches the second surface of the lead frame to a tape, and performs a punching process to cut off the neck portion of the lead so as to form a plurality of conductive blocks disposed independently on the periphery of the die pad. The method further provides a chip having its back surface attach to the first surface of the die pad, and provides electrical connection between the bonding pad and the first surface of the conductive block by using a plurality of bonding wires. Further, the method performs an encapsulating process to encapsulate the chip, the bonding wires, the die pad, and the first surface of the conductive block.

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base, a conductive trace and a through-hole between its top and bottom surfaces. The through-hole includes a top sidewall portion adjacent to the top surface and a bottom sidewall portion adjacent to the bottom surface. The conductive trace includes a pillar at the top surface and a routing line at the bottom sidewall portion. An electroplated contact terminal on the pillar extends above the base, and an electroplated connection joint in the through-hole contacts the routing line and the pad. Preferably, the connection joint is the only metal in the through-hole. A method of manufacturing the assembly includes simultaneously electroplating the contact terminal and the connection joint.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for milling the substrate of a semiconductor device to expose a selected region in the substrate, wherein the semiconductor device has a grid formed in the device to provide lateral and depth position indication during an etch/milling process. In an example implementation, the grid is three dimensional and is used during device analysis for navigation while removing substrate to access a selected circuit area via the backside of flip-chip device. As substrate is removed, the tools are aligned as indicated by the grid.

Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

Abstract: A multilayer structure is provided which suppresses hillock formation due to post-heat treatment steps in thin aluminum films deposited on other substrates by sandwiching the aluminum film between thin layers of aluminum titanium nitride. The first aluminum titanium nitride layer acts as a compatibilizing layer to provide a better match between the coefficients of thermal expansion of the substrate and aluminum metal layer. The second aluminum titanium nitride layer acts as a cap layer to suppress hillock formation.

Abstract: A semiconductor device with advanced functions and an improved factor of effective mounting area comprises a semiconductor chip on which an IC or the like is formed; a plurality of external connector electrodes having a block form which are connected with a plurality of electrodes of the semiconductor chip, arranged near the circumference of the semiconductor chip at a prescribed distance from the semiconductor chip, and composed of a substrate other than the semiconductor chip; a wiring substrate which is arranged face to face with the semiconductor chip and the external connector electrodes, and a wiring pattern for electrically connecting each electrode of the semiconductor chip with the external connector electrodes is formed on the surface. Connectors connect the wiring pattern with both electrodes of the semiconductor chip and external connector electrodes and form a prescribed space between the wiring substrate and the semiconductor chip. A method of manufacturing such devices is also disclosed.

Abstract: An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa.

Abstract: A power semiconductor device having an improved high breakdown voltage and improved productivity, and a fabrication method thereof are provided. The power semiconductor includes a collector region of a first conductivity type formed in a semiconductor substrate, a base region of second conductivity type formed in the collector region, and an emitter region of the first conductivity type formed in the base region. A channel stop region is formed being spaced a predetermined distance from the base region. An insulative film, a semi-insulating polycrystalline silicon (SIPOS) film, and a nitride film patterned respectively to expose the emitter region, the base region, and the channel stop region are sequentially deposited on the semiconductor substrate. A base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region are formed.

Abstract: Disclosed is a dicing method using a dicing apparatus comprising at least a chuck table holding workpiece attached a frame via an adhesive tape, and dicing means for cutting a workpiece into small square pieces. The workpiece is cut into small square pieces in the state of being held in the frame, and a blow of air is ejected from the surface of the chuck table to the diced workpiece to expand the adhesive tape in the semispherical form. As a result, adjacent square pieces are put apart from each other, thus making adjacent square pieces even if they remain partly contiguous to be forcedly put apart from each other.