Patents Examined by D. Monin
  • Patent number: 6072208
    Abstract: In a dynamic random access memory (DRAM), a step produced by forming a stacked capacitor can be prevented from being produced and increased, thereby facilitating the patterning of an upper layer (wiring, etc.). Further, the pattern layout can be made with freedom and the DRAM itself can be highly integrated. This dynamic random access memory is constructed such that stacked capacitors (C.sub.1), (C.sub.2) composed of accumulation node electrodes (7a), (7b), a dielectric layer (8) and a sub-plate electrode (9) are formed on the under layers of a switching element (Tr1) composed of a word line (4a) and two source-drain regions (5a), (5b) and a switching element (Tr2) composed of a word line (4b) and two source-drain regions (5a), (5c).
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: June 6, 2000
    Assignee: Sony Corporation
    Inventor: Toshiyuki Nishihara
  • Patent number: 5471077
    Abstract: A high electron mobility transistor (HEMT) includes a diffusion barrier (22) to prevent gate metal (20) diffusion into the substrate (12) during fabrication and a sacrificial platinum alloy layer (30) forms the Schottky barrier. A method of forming a HEMT includes forming a diffusion barrier of titanium nitride on a platinum layer and applying sufficient heat to cause the platinum layer to alloy with the gallium arsenide layer forming a platinum gallium and platinum arsenide alloy layer and Schottky barrier. Since all platinum is consumed, this method permits precise control of the thickness of the gate layer and eliminates diffusion of the platinum gate layer into the gallium arsenide layer during later processing steps.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: November 28, 1995
    Assignee: Hughes Aircraft Company
    Inventor: Marko Sokolich
  • Patent number: 5459348
    Abstract: The present invention provides a heat sink and electromagnetic interference shield assembly for a plurality of semiconductor elements. The semiconductor elements are connected with other circuit elements to form an electrical circuit. Each semiconductor element has a metal portion for dissipating heat generated by the semiconductor element. The metal portion also emits electrical energy as a result of the operation of the semiconductor element thereby causing unwanted electromagnetic interference. The assembly comprises an insulator attached to the meted portion of the semiconductor element and a substrate for mounting the plurality of semiconductor elements. The insulator is of a thermally conductive material to facilitate the conduction of thermal energy away from the semiconductor element. The substrate has a metal base layer, a middle insulating layer, and a plurality of metal mounting areas for mounting the plurality of semiconductor elements.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: October 17, 1995
    Assignee: Astec International, Ltd.
    Inventor: David A. Smith
  • Patent number: 5455447
    Abstract: A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42).
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: October 3, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Louis N. Hutter, Joe R. Trogolo
  • Patent number: 5424575
    Abstract: A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: June 13, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Katsuyoshi Washio, Tohru Nakamura, Takahiro Onai, Masatada Horiuchi, Takashi Uchino
  • Patent number: 5408117
    Abstract: A semiconductor device comprises a first conductivity type semiconductor layer and a second conductivity type well region which is formed on the semiconductor layer. The well region includes a first semiconductor region of a first depth and a second semiconductor region of a second depth deeper than the first depth which is provided in the central portion of the first semiconductor region. The ratio of the first depth to the second depth is settled in a range from 0.85 to 0.95 in order to increase the breakdown voltage of the semiconductor device.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: April 18, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akio Uenishi
  • Patent number: 5394011
    Abstract: A package structure in which conductive layers are provided on the lower surface of a circuit substrate provided with a semiconductor element mounted on the upper surface thereof, which conductive layers are connected to a conductive seal portion via conductive through holes, whereby both satisfactory air-tightness and satisfactory electromagnetic shielding characteristics of the package structure can be obtained. Projections consisting of high-temperature solder are formed as externally connecting electrodes, whereby a surface packaging operation can be carried out smoothly.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: February 28, 1995
    Assignees: Iwaki Electronics Co. Ltd., Fuji Electrochemical Co., Ltd.
    Inventors: Hiroyasu Yamamoto, Takayuki Konuma, Akira Shika, Hiroyoshi Suzuki, Masanori Katouno, Kaori Sato
  • Patent number: 5381025
    Abstract: An insulated gate thyristor (IGTH) (40,80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed without source diffusions to create a lateral MOSFET (T.sub.5) that can turn off the latched IGBT.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: January 10, 1995
    Assignee: Ixys Corporation
    Inventor: Nathan Zommer
  • Patent number: 5350944
    Abstract: Electrical quality insulating films on n-type and p-type diamond substrates are provided in which an insulating film such as a silicon dioxide film is deposited onto the exposed face of a diamond substrate, such as by chemical vapor deposition. Forming a conducting layer atop the silicon dioxide allows the creation of a metal-oxide-silicon device with which semiconductor carriers can be controlled through the application of a bias voltage to the conductor surface.
    Type: Grant
    Filed: February 20, 1992
    Date of Patent: September 27, 1994
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael W. Geis, Daniel L. Smythe
  • Patent number: 5336922
    Abstract: In a semiconductor device including charge storage capacitors, each of which includes a patterned electrode having electrode side and top surfaces, a dielectric film on the side and top surfaces, and a covering electrode on the dielectric film, the patterned electrode is composed of a lower silicon layer having layer side and top surfaces and an upper silicon layer lying on the layer side and top surfaces and having the electrode side and top surfaces. The dielectric film may be in direct contact with the electrode side and top surfaces. In this event, the lower silicon layer is preferably doped to a lower concentration between 10.sup.15 and 10.sup.18 atoms per cubic centimeter and the upper silicon layer, to a higher concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. Alternatively, a barrier metal film may be interposed between the dielectric film and the electrode side and top surfaces.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: August 9, 1994
    Assignee: NEC Corporation
    Inventor: Mitsuru Sakamoto
  • Patent number: 5334855
    Abstract: A light emitting diode including a carrier injection layer of semiconductor material, such as diamond, and a light emitting layer of polycrystalline phosphor, such as zinc oxide, positioned to form a diode junction therebetween. The semiconductor material being selected to have a wider bandgap than the polycrystalline phosphor and the materials being further selected to minimize the discontinuities at the junction which would cause energy spikes.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: August 2, 1994
    Assignee: Motorola, Inc.
    Inventors: Curtis D. Moyer, James E. Jaskie, Ronald N. Legge
  • Patent number: 5332922
    Abstract: A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: July 26, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Oguchi, Masamichi Ishihara, Kazuya Ito, Gen Murakami, Ichiro Anjoh, Toshiyuki Sakuta, Yasunori Yamaguchi, Yasuhiro Kasama, Tetsu Udagawa, Eiji Miyamoto, Youichi Matsuno, Hiroshi Satoh, Atsusi Nozoe
  • Patent number: 5332914
    Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.
    Type: Grant
    Filed: October 17, 1991
    Date of Patent: July 26, 1994
    Inventor: Emanuel Hazani
  • Patent number: 5321303
    Abstract: A method for manufacturing a semiconductor device using inclined stage of a dicing saw in order to cut the semiconductor substrate obliquely with respect to the depthwise direction. When a plurality of semiconductor chips diced obliquely are connected, a degree of connecting accuracy is increased, and it is possible to realize a contact-type image sensor of high resolving power and high accuracy.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: June 14, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Yukito Kawahara, Hiroshi Mukainakano, Satoshi Machida
  • Patent number: 5311048
    Abstract: Herein disclosed is a semiconductor integrated circuit device, in which a buffer circuit having a MISFET of a second conduction type and arranged in a first region of the principal plane of a semiconductor substrate of a first conduction type is supplied with a first supply voltage and in which an internal circuit having a complementary MISFET and arranged in a second region of the principal plane of the semiconductor substrate different from the first region is supplied with a second supply voltage independent of the first supply voltage at least over the semiconductor substrate and having a potential equal to that of the first supply voltage. The MISFET of the buffer circuit is formed in the principal plane of a well region of a first conduction type formed in the principal plane of the semiconductor substrate. Between the well region of the first conduction type and the semiconductor substrate, there is formed a separating region for separating the two electrically.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: May 10, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshiro Takahashi, Kazuo Koide
  • Patent number: 5309011
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: May 3, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Patent number: 5304835
    Abstract: A semiconductor device comprising a memory cell matrix array wherein transistors formed on the outer edge of the memory cell matrix array are inferior in performance compared to the transistors comprising the operating memory cell matrix array because their transistor active regions shrink during semiconductor device fabrication. To avoid this problem, a dummy region is formed around the operating memory cell matrix array. The dummy region contains impurity regions formed at substantially the same density as the transistors comprising the operating memory cell matrix array. Thus, the transistors located on the outer edge of the operating memory cell matrix array function in the same manner as transistors formed within the operating memory cell matrix array. As a result, all the transistors of the operating memory cell matrix array have uniform performance.
    Type: Grant
    Filed: May 18, 1992
    Date of Patent: April 19, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Kaori Imai, Noboru Itomi
  • Patent number: 5300810
    Abstract: The disclosure is directed to an improved circuit and method which utilizes a plurality of generally planar diamond substrate layers. Electronic circuit elements are mounted on each of the substrate layers, and the substrate layers are disposed in a stack. Heat exchange means can be coupled generally at the edges of the substrate layers. In a disclosed embodiment, a multiplicity of generally planar diamond substrate layers and a multiplicity of generally planar spacer boards are provided. Each of the substrate layers has mounted thereon a multiplicity of electronic elements and conductive means for coupling between electronic elements. In general, at least some of the electronic elements on the substrate layers comprise integrated circuit chips. The substrate layers and spacer boards are stacked in alternating fashion so that spacer boards are interleaved between adjacent substrate layers.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: April 5, 1994
    Assignee: Norton Company
    Inventor: Richard C. Eden
  • Patent number: 5296745
    Abstract: A semiconductor device having a moisture barrier comprises a semiconductor substrate, a plurality of bonding pads arranged along at least one side of the semiconductor substrate, and an insulating film provided between at least one side of the semiconductor substrate and the bonding pads opposite to that side, and provided with means for preventing incursion of moisture, thereby to prevent moisture from being absorbed from the chip side surface. Further, there is also disclosed a method of manufacturing such a semiconductor device, which comprises the steps of forming an insulating film on a semiconductor wafer, forming a plurality of bonding pads arranged along dicing lines of the semiconductor wafer, and forming a contact hole or a via hole in the insulating film, and forming at the same time, a groove structure so that it is arranged between the dicing lines and the plurality of bonding pads.
    Type: Grant
    Filed: March 25, 1991
    Date of Patent: March 22, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Shirai, Satoshi Shibahara
  • Patent number: 5296744
    Abstract: A lead frame assembly characterized by alternating high and low wire loops which connect the attach pads of an integrated circuit die to the conductive fingers of the lead frame. The alternating loops reduce the likelihood that adjacent loops will short out due to twists in the wires or due to connecting wire "sweep" caused by subsequent plastic encapsulation. A number of high loops can be attached before the formation of the first low loop or vice versa. Alternately, the high and low wire loops can be attached in an alternating fashion.
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: March 22, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Louis H. Liang, Sang S. Lee