Abstract: The table cloth matrix comprises a semiconductor substrate, wherein there are contained in deep layers, under strips of field oxide, source lines and drain lines parallel to one another, areas of floating gate connecting said source lines and drain lines and control gate lines, parallel to one another and perpendicular to said source lines and drain lines, in a condition superimposed over said floating gate areas. Each source line is alternated with two drain lines separated by an insulation zone, so that each drain line is associated with a single row of matrix cells.

Abstract: A high voltage, high speed Schottky diode has an electrode of aluminum or like Schottky barrier metal formed on a semiconductor region to create a Schottky barrier therebetween. Also formed on the semiconductor region is a extremely thin resistive layer of, typically, oxidized titanium surrounding the barrier metal electrode and electrically connected thereto. The resistive layer also creates a Schottky barrier at its interface with the semiconductor region and serves to expand the depletion region due to the barrier metal electrode, thereby preventing the concentration of the electric field at the periphery of the barrier metal electrode and so enhancing the voltage withstanding capability of the diode.

Abstract: A method of forming a high density semiconductor structure including one or more buried metal layers. One or more metal layers may be formed on a first semiconductor substrate, with the metal layer or layers being insulated from one another and from the substrate. One or more metal layers may be formed on the surface of a second substrate which may or may not be a semiconductor substrate. The topmost metal layers, either or both of which may have an insulating layer thereon, are placed in contact and heated in an oxidizing ambient atmosphere to form a bond therebetween. One or more vias connect the buried metal layers to the active devices in the substrates. The buried metal layers may form buried power and ground planes and buried metallization patterns for device interconnection.

Abstract: A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film

Abstract: A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

Abstract: An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

Abstract: A connection structure between lead frames and a base plate of aluminum nitride, to be applied as a connection structure between components of a semiconductor apparatus, has a base plate made of a sintered body of aluminum nitride on which a semiconductor device is to be mounted. The lead frames are made of iron alloy containing nickel in 29 wt. % and cobalt in 17 wt. %. A silver solder is used for joining the base plate and the lead frames. A surface of the lead frame to be joined to the base plate is clad with a stress relief layer of oxygen-free copper of a high plastic deformability to relieve, by its plastic deformation, a thermal stress caused by a difference between a thermal expansion coefficient of the aluminum nitride base plate and that of the lead frame in a cooling process at the time of soldering. Preferably, only a portion of each lead frame to be joined to the base plate comprises an inner layer of an iron alloy containing 29 wt. % of nickel and 17 wt.

Abstract: A semiconductor device having a grooved field plate(s), a grooved field limiting ring(s) or a combination of a grooved field plate(s) and grooved field limiting ring(s) is disclosed. The grooved modification of the conventional semiconductor results in an increased break-down voltage over the conventional semiconductor device. A method for manufacturing the grooved semiconductor device is disclosed.

Abstract: A symmetrical blocking high breakdown voltage semiconductor device in which the lower junction termination is brought to the upper surface is fabricated by diffusing first and second regions of a first conductivity type into an upper surface of an epitaxial layer of a second conductivity type disposed on a substrate, and forming a groove having sloped sidewalls in the upper surface such that the groove extends through the second diffused region, the epitaxial layer and into the substrate. A thin layer of impurities of the first conductivity type is implanted into the sidewalls, and the impurities are electrically activated to form a low resistivity path that connects the substrate to the second diffused region. Subsequently, the semiconductor device may be separated from the wafer by cutting the wafer at the groove. The manufacturing process enables substantially complete fabrication of a plurality of devices while still in wafer form, thereby avoiding the inconvenience of processing individual dice.

Abstract: A field effect transistor chip for connection to a microstrip transmission line includes a semiconductor substrate, a field effect transistor formed in the substrate, source, gate, and drain electrodes disposed at least partially on the substrate, the gate and source electrodes forming an air bridge, and gate and drain beam leads extending from the substrate for electrical connection to the conductors of a microstrip transmission line. The microstrip transmission line includes dielectric substrates on which substantially uniform width conductors are disposed, the substrates being separated by a gap in which the transistor chip is disposed. The beam leads may be unitary with the electrodes of the chip or with the conductors of the transmission line.

Abstract: The disclosure relates to a solar array with interconnects wherein an array is formed by providing a pair of spaced flexible aluminum foil sheets which are electrically insulated from each other and wherein semiconductor spheres extend through one of the sheets and are electrically coupled to both sheets. A plurality of such arrays are formed in a strip and the individual arrays are separated by placing shims at the scribe locations and scribing thereover so that one of the sheets has an edge extending outwardly for connection to a sheet of another array. In this manner, large solar panels can be formed from a plurality of interconnected arrays in a reel-to-reel embodiment.

Abstract: A semiconductor device comprises a semiconductor substrate of a low impurity concentration, a channel region formed on the substrate and having a low impurity concentration, a source region formed on the channel region and having a high impurity concentration of a conductive type opposite to that of the substrate, and a drain region formed on the channel region and having a high impurity concentration of a conductive type opposite to that of the substrate. The source region and the drain region are arranged along a predetermined direction along the substrate. The semiconductor device further includes an accumulating gate region of a conductive type same as that of the substrate, so formed as to surround either one of the source region and drain region, leaving a part of said channel region sandwiched between the source region and the drain region.

Abstract: A compact CMOS structure and method for fabricating the structure are disclosed. In one embodiment of the invention the structure includes a P-type surface region in a silicon substrate surrounded by a field oxide which extends, at least in part, above the surface of the substrate. A polycrystalline silicon sidewall frame is formed at the sidewall of the field oxide and a gate insulator is formed over both the polycrystalline silicon frame and the silicon surface region. A common gate electrode is formed which traverses the frame and the surface region. P-type source and drain regions are formed in the polycrystalline silicon frame on opposite sides of the gate electrode and N-type source and drain regions are formed in the surface region on opposite sides of the gate electrode.