Abstract: A semiconductor device comprises a semiconductor body (1) of silicon having a monolithic integrated circuit with a field oxide pattern (2) having at least one protection element (T2) having at least one active zone (4) of a first conductivity type, which adjoins at least in part the field oxide (2) and forms with the adjoining silicon region (5) of the second opposite conductivity type a pn junction (6). The active zone (4) is contacted with an electrode layer (7), which is connected to a point (G) of the semiconductor device to be protected against static discharge. The electrode layer (7) consists of a metal silicide. According to the invention, the metal silicide (7) also extends onto the field oxide (2) adjoining the active zone (4) over a certain distance, which is preferably at least 0.5 .mu.m.

Abstract: Disclosed is a floating gate EPROM cell wherein a trench is formed in and divides the semiconductor substrate into two portions. Separated source and drain regions are formed in one portion and contact one side of the trench region, and a control gate region is formed in the second portion and contacts the opposite side of the trench. A first insulating film covers the source, drain, trench regions and part of the control gate region, a portion of which is covered by a first polycrystalline silicon film which forms the floating gate. A second insulating layer covers the first polycrystalline silicon film and also a portion of the control gate region, which, in turn, is covered by a second polycrystalline silicon layer which extends beyond the second insulating layer into electrical contact with the control gate region. Thus, a control gate is provided both above and below the floating gate.

Abstract: Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film.

Abstract: An improved standard cell logic chip, of the type which contains one to fifteen thousand standard logic cells that are disposed in rows on a substrate, and has cell interconnect channels of different widths between the rows, also includes fast change logic cells which are sparsely distributed in the rows of standard logic cells. Each fast change cell selectively performs any one of several logic functions. These fast change logic cells are formed from the same stacked conductive and insulative layers as the standard logic cells; however, in the fast change cells, all conductive and insulative layers which are below at least the mid level in the stack of layers have respective patterns which are identical in every fast change cell. Only the remaining conductive and insulative layers in the fast change cells have respective patterns which differ from one fast change cell to another, and they select the logical functions which the fast change cells perform.

Abstract: A high-speed semiconductor device comprising emitter potential barrier layer disposed between an emitter layer and a base layer, a collector layer, and a collector potential barrier layer disposed between the base layer and the collector layer. The collector potential barrier layer has a structure having a barrier height changing from a high level to a low level along the direction from the base layer to the collector layer, whereby, even when no bias voltage is applied between the collector layer and the emitter layer, a collector current can flow through the device.

Abstract: There is disclosed a field effect transistor comprising a channel layer formed of GaInAs and provided with a planar dope layer doped with an impurity in the form of a two-dimensional thin plane a cap layer and a buffer layer formed respectively in contact with the upper and lower faces of the channel layer, the cap layer and buffer layer being formed of GaInAs whose In composition ratio is lower than that of the channel layer first and a second semiconductor layers formed respectively in contact with the cap layer and the buffer layer, first and second semiconductor layers being formed of GaInAs whose In composition ratio is lower than GaAs or the cap layer and the buffer layer.

Abstract: In an integrated circuit in which the capacitances of a pair of capacitors are arranged to be in a ratio k by choosing the areas of corresponding plates of the two capacitors to be in this ratio, and the plates are shaped so that the total lengths of their boundaries are also in this ratio so as to reduce the sensitivity of k to manufacturing tolerances, this sensitivity is further reduced by arranging that the ratios between the numbers of 90.degree. corners exhibited by the respective plates, and the numbers of 270.degree. corners exhibited by the respective plates, are each also substantially equal to k. To make this possible an aperture is arranged to be present in each plate.

Abstract: The invention relates to the hermetic packaging of typically one or two dice for high power density applications. The package, which is intended for surface mounting to a heating sinking substrate, is particularly compact. Compactness in surface mount applications is measured as a minimum ratio of package area to die area. In accordance with the invention, compactness is achieved by using a novel vertically developed design in which the electrical connections lie within vertical extensions of the die boundaries giving a package to die ratio of less than 2 to 1.

Abstract: A thin film phototransistor is provided having a field effect transistor structure where at least one end of the gate electrode is not overlapped with an electrode neighboring the end. Such a thin film phototransistor has: (1) a function as a photosensor and a switching function; (2) a high input impedance; (3) a voltage control function; and (4) a high photocurrent ON/OFF ratio. This thin film phototransistor can be used independently or together with a thin film transistor for picture elements of a one-dimensional or two-dimensional photosensor array, producing satisfactory results.

Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Abstract: A novel BICMOS output buffer is taught including circuit means for firstly discharging the bases of the bipolar pull up and bipolar pull down transistors, and secondly to connect the base of an output transistor to its emitter when that output transistor is conducting, thereby insuring maximum voltage swing of the output voltage. The circuit means comprises an MOS transistor for discharging the base of an output transistor, and a depletion mode MOS transistor for connecting the base of an output transistor to its emitter. By utilizing MOS and depletion mode transistors, a significant area advantage is achieved, particularly when the MOS and depletion mode transistors are merged.

Abstract: An input protection structure for integrated circuits to be connected between an input and a reference potential includes a resistor. At least one transistor has a collector connected to the input, a base connected through the resistor to the reference potential, and an emitter connected to the reference potential. A semiconductor substrate has a first conduction type. The collector is in the form of a buried collector of a second conduction type in the semiconductor substrate. The base is in the form of at least one doped zone of the first conduction type having a base connection. The emitter is in the form of a doped zone of the second conduction type having an emitter connection. The resistor is in the form of at least one further doped zone of the first conduction type being connected to the emitter exclusively through the emitter connection and being connected to the base exclusively through the base connection.

Abstract: A light emitting diode device comprises an n type silicon carbide substrate having first and second major surfaces opposite to each other at least inclined at a predetermined angle not less than 3.degree. from a {0001} plane, an n type silicon carbide layer grown on the first major surface, a p type silicon carbide layer grown on the n type silicon carbide layer, a p type ohmic electrode formed on a partial area of the p type silicon carbide layer, and an n type ohmic electrode formed on a partial area of the second major surface. The diode element has a substantially trapezoidal form in a cross section orthogonal to the first major surface. The diode element has the side of the p type silicon carbide layer broader than the side of the second major surface and is supported at the side of the type silicon carbide layer fixed to a supporting stem.

Abstract: In a semiconductor memory of the invention, the source or drain of a transfer gate MOS transistor is electrically connected to a charge storage first conductive layer through a third conductive layer.

Abstract: A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.

Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tub, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

Abstract: A field effect transistor includes a semiconductor substrate having a first conduction type and functioning as a drain of the field effect transistor, and a back gate region formed in the semiconductor substrate and having a second conduction type opposite to the first conduction type. The field effect transistor also includes a source region formed in the back gate region and having the first conduction type, an insulator film formed on the semiconductor substrate and having first and second windows, and a gate electrode covered by the insulator film and located so that a channel is formed in the back gate region. Further, the field effect transistor includes a guard region formed in the semiconductor substrate and located close to the back gate region. The guard region has the second conduction type, and has a first portion located on a first side of the guard region facing the back gate region and a second portion located on a second side opposite to the first side.

Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.

Abstract: A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed.

Abstract: A semiconductor integrated circuit includes a semiconductor chip having a plurality of pad electrodes fixed in a lead frame. Electrical leads connected to the chip include outer lead portions, external to the lead frame, and inner lead portions, internal to the lead frame and electrically connected to the semiconductor chip. At least one lead is a dummy lead, providing additional space in the lead frame. Due to the extra space, the inner lead portions may have various shapes, including large leads, or branched leads, for elimination power noise.