Abstract: A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed.

Abstract: A complementary input circuit with a nonlinear front end is used to transfer the state of an external input to the internal signal lines of an intetraged circuit chip such as a dynamic or static RAM. The combination of a nonlinear front end and a "partially" cross-coupled complementary latch provide good level detection.

Abstract: An I/O control circuit is provided which is of the type that receives two inputs such that four sets of input conditions to the circuit are defined. A first set of input conditions establishes a low impedance path from the circuit output to the positive supply. A second set of input conditions establishes a low impedance path from the output to the negative supply, or ground. A third set of input conditions establishes a high impedance path from the output to both the positive and the negative supply. And, in accordance with the present invention, "pull-up" means is connected to the output such that the fourth set of input conditions establishes a path to the positive supply, the path having an impedance which is intermediate that of the low impedance and the high impedance. Alternatively, "pull-down down" means is connected to the output such that the fourth set of input conditions establishes an intermediate impedance path to the negative supply.

Abstract: There is disclosed a sense amplifier characterized by comprising a pull-up circuit. The pull-up circuit comprises a first transistor arranged between the first of a pair of output nodes and a pull-up power source potential node, and a second transistor arranged between the second of the pair of output nodes and the pull-up power source potential node. The gate of the first transistor is connected to the second output node and the gate of the second transistor is connected to the first output node.

Abstract: An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.

Abstract: An integrated circuit includes a plurality of threshold-value compensatory programmable elements integrally incorporated into a semiconductor integrated circuit, wherein, during the inspection process after assembly, the programmable elements store stationary data related to varied threshold voltages occurred during assembly process so that the varied substrate bias voltages can be restored to an ideal level by applying compensations as required. This circuit is extremely advantageous in that it effectively compensates for even the slightest variation of the threshold voltage in the integrated circuit using its extremely simplified circuit configuration, and in light of the conventional tendency in which redundant circuits containing a variety of chip parts each having a substantial area are used, against the needs for high-density part installation, the circuit embodied by the present invention effectively and securely provides means for realizing higher yield of monolithic semiconductor integrated circuits.

Abstract: The invention relates to a charge detector, more particularly for reading binary information in a CTD. The detector includes a flipflop having two cross-coupled MOS transistors and two MOS transistors acting as loads. The signal to be read and the reference signal are supplied to the gates of the loads. The junctions between the driver transistors and the loads are connected to reset transistors. The drains of the loads are applied to a (fixed) supply voltage and the sources of the driver transistors are applied via a switching transistor to the supply voltage return. The circuit arrangement is operated so that before the activation of the flipflop the said junctions are set to a signal-dependent preadjustment. When the switching transistor is then energized, the flipflop will be in the correct stage with a higher degree of reliability and without being influenced by clock cross-talk.

Abstract: An emitter-coupled multiplexer has all transistors directly controlled by one select signal in parallel with transistors directly controlled by other select signals. Thus, in a 3:1 multiplexer (100), a first select signal (S0) directly controls one transistor (Q13); this transistor is in parallel with another transistor (Q14) which is directly controlled by a second select signal (S1). The second select signal also directly controls another transistor (Q15) in the same network (102). This transistor is in parallel with a transistor directly controlled by an input signal (I1) which is thus masked when the second select signal is activated. The second select signal also controls (at Q16 and Q18) subnetwork selection in another current network (104) of the multiplexer. The disclosed arrangement permits the multiplexer function to be implemented with a reduced transistor count and only two current sources in two-level series gating.

Abstract: A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q.sub.1, Q.sub.2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M.sub.3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q.sub.2. The threshold voltage of an NMOSFET M.sub.2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M.sub.3 in the absence of the substrate effect, and the channel conductance W.sub.N /L.sub.N of the NMOSFET M.sub.3 is so set that the threshold voltage V.sub.LT1 of the CMOS inverter and the practical threshold voltage V.sub.LT2 of the NMOSFET M.sub.3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.

Abstract: The majority circuit has an (n+1)/2-notation counter circuit comprising a plurality of cascade-connected binary counters. An odd number of n-bit serial data are counted by the counter circuit, and an output of the binary counter of the last stage is taken out as a majority output of the majority circuit.

Abstract: A self-timed transition detector is provided that responds to a change in the logic level of a signal by generating a change-indicator flag. The change-indicator flag is held active until an event initiated by the change-indicator flag has been completed. Completion of the event cancels the change-indicator flag, thereby verifying the completion of the event.

Abstract: An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption.A first switch is provided between a refresh voltage terminal and a true circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.

Abstract: A semiconductor memory device of the invention is switched to an operation mode or a standby mode in response to a control signal. When the control signal indicates the standby mode, a voltage converter circuit becomes inoperative, and an external power source voltage is directly supplied to an internal circuit (e.g., a memory circuit). However, in the standby mode the internal circuit has low power consumption, and the voltage converter circuit has no power consumption, thus rendering total power consumption of the semiconductor device low. When the control signal indicates the operation mode, the voltage converter circuit drops the external power source voltage and supplies it to the internal circuit. Thus, no hot electrons are generated in elements constituting the internal circuit (e.g., CMOS transistors), and degradation of the elements is prevented.

Abstract: A bootstrapped CMOS driver circuit capable of driving large capacitance loads with small internal delays. Higher driving capability is achieved by using only n-channel transistors at the output and overdriving the transistors during the transitions. A total internal delay of less than one nanosecond for a driver may be provided with 100 ohms compatible output impedance.

Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Abstract: A redundancy enable/disable circuit for enabling and disabling subsequently the use of redundant elements includes first through third P-channel MOS transistors, an N-channel MOS transistor, an enable fuse, and a disable fuse. The enable fuse is blown so as to enable the use of the redundant elements, and the disable fuse is blown subsequently to disable use of the redundant elements.

Abstract: Improved access to programmable logic arrays is provided by continuously asserting and negating a latch inputs control signal, continuously asserting and negating a control signal which discharges a first logic section of the array to provide frequent, current inputs to a second logic section of the PLA and discharging the second section of the PLA only upon receipt of an access request. In the case of asynchronous access, it is also necessary to generate a synchronized data strobe from the unsynchronized one and to generate an acknowledge signal to indicate the presence of valid output data. The disclosed method and apparatus provide access which has a short access time and which also provides outputs which reflect relatively current states of the inputs thereto.

Abstract: A transistor circuit with hysteresis operation, which is formed with a detector part and selector part. The detector part detects a change in the level of an input signal according to one of first and second threshold levels, and generates an output signal having a level corresponding to the input signal. The level of the input signal is changed between a first level and a second level which is lower than the first level. The first and second threshold levels fall within a range defined between the first and second levels. The selector part selects one of the first and second threshold levels in accordance with the level of the output signal, and applies the selected one threshold level to the detector part.

Abstract: A two-level series gating complementary output master-slave D-type flip-flop (100) with multiplexed input incorporates a novel current-splitting network (108). The flip-flop includes a master latch (102), a slave latch (104) and a 2:1 multiplexer (106) incorporated into the master latch. The multiplexer includes a pair of matched, emitter-coupled, collector-uncoupled transistors (Q12 and Q13), the bases of which are tied to a reference voltage (VBB2). When a clock pulse (CP) is low, substantial network current flows through both matched transistors. This arrangement allows the circuit function to be implemented with a reduced transistor count and only two current sources. The master latch output (QM) is determined by the voltage at the base of an output transistor (Q21), which voltage is determined by the presence or absence of a current through a load resistor (RL1).

Abstract: A differential cascode voltage switch (DCVS) logic circuit in which different DCVS logic blocks are connected in parallel to the output lines. Selection transistors connected to each logic block complete the conductivity path to ground. Only one selection transistor is selected at a time to thereby select the associated logic blocks. The circuit can be improved by merging portions of the different logic blocks which are identically connected to the output lines.