Abstract: A system for multiplexed transfer of data between plural blocks interconnected by a two-way data bus of a predetermined number of bus lines provides for simultaneous and parallel transfer over the plural bus lines of plural data bits, up to the same, maximum predetermined number of the bus lines. Each parallel data bit transfer is selectively controllable with respect both to the number and the direction of transfer of the individual data bits over the respectively corresponding bus lines of the two-way data bus. Each block comprises a plurality of internal circuit cards, an internal bus of plural bus lines, of the same predetermined number, respectively connected to plural internal circuit cards of the block, and plural two-way transfer gates respectively associated with and selectively operable for interconnecting the corresponding bus lines of the internal bus and the two-way data bus.

Abstract: A graphics buffer (22) for storing information describing pixels that represent an image. The graphics buffer includes Surface Buffer Modules (32) that include a first memory (46) for storing pixel surface information, such as color, for a plurality of pixels. The Surface Buffer Modules, each further include a first processor (44) coupled to the first memory for modifying pixel information read therefrom and for storing said modified pixel information back into the first memory. The graphics buffer may also include at least one Control Buffer Module (34) that includes a second memory (46') for storing other pixel information, such as pixel flags, and a second processor (44') for modifying the other pixel information. A pixel bus (38) is coupled in common between the Surface Buffer Module and the at least one Control Buffer Module for conveying pixel-related information, including pixel data, pixel addresses, and the results of pixel tests, therebetween.

Abstract: A new controller transfers data directly between the register of an I/O port and an ALU register in an operation that takes only one phase of a two-phase clock cycle. A transfer between an ALU register and main memory is also performed in one phase, and the entire transfer can be accomplished in one clock cycle. A connection is also provided between the ALU registers and the flag register, and when the incoming byte is a status byte, the controller can transfer the byte to the flag register where it can control the next instruction execution.

Abstract: An optical head device for projecting a light beam on a recording medium to record data thereon or reproduce the recorded data comprises an optical system for forming a beam spot of a specified diameter on the surface of the recording medium, and a transparent contact member disposed at a light emanating portion of the system for the recording medium to come into direct sliding contact therewith. Accordingly, when the contact member moves relative to the recording medium, the dust adhering to the surface of medium is removed by the contact member to assure a recording or reproduction operation free of errors.

Abstract: A model railroad cattle car sound effects system includes a speech synthesis circuit (FIG. 6) for "playing" selected cow voices stored as digital data in an EPROM (160). In a random mode of operation, a state generator (30) provides a pseudo-random count that is used to select among four different calm cow voices, one of which is silence. The resulting audio output is perceived as random contented cow sounds. A pendulum motion detector (FIG. 8) provides an indication of lateral motion of the system. An up/down motion counter (40) maintains a motion count reflecting the level of excitation of the system (and the cows). The motion counter increments responsive to motion, and decrements gradually in the absence of detected motion. A motion count of at least four invokes a triggered mode of operation, in which the counter output is used to select among four different excited cow voices. The resulting audio output imitates increasingly agitated cows as the motion count further increases.

Abstract: A method and circuitry for controlling priority of devices contending for access to a data communications link. Each device capable of contending for access contains a priority register which indicates the relative priority of every device capable of contending for access. After gaining access to the link, a device may optionally signal to all devices to update priority. When priority is updated, the device signaling priority update is moved to lowest priority. Inhibiting the signal to update priority permits a device to maintain priority. Systems using the method may be configured with a fair arbitration protocol (least recently accessed has highest priority), with fixed priority protocol, or with priority protocols that can be modified in real time.

Abstract: Provides a method for measuring the busy utilization time for I/O channel used by any of plural operating systems (OSs) in a CEC. The measured utilization time for any OS excludes the time shared channels are utilized by other OSs during a measurement period. A channel measurement facility (CMF) is provided in the I/O subsystem hardware and microcode for each of the OSs in the I/O subsystem. The CMF is logically constructed because it uses only a small portion of I/O resources already existing in a CEC by adding microcode to control these resources to perform the time measurement function. The resources for a logical CMF including the partial use of: an I/O processor to store identifiers of an assigned OS, the partial use of channel processors controlling channels selected by the assigned OS during a measurement period, the local storage of each I/O processor, and OS storage needed for communicating the measurement data from the CMF to the OS.

Abstract: A method for accelerating the writing of data to a Z buffer including the steps of reading the Z value presently stored at a position in the Z buffer; writing a new Z value to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote a new Z value to a position in the Z buffer, writing the Z value read back to the position in the Z buffer if the result of a last available comparison in a sequence of comparisons wrote the Z value read back to a position in the Z buffer, and comparing the Z value read from the position of the Z buffer with the new Z value; and rewriting the correct value to the Z buffer if the comparison of the Z value read from the position of the Z buffer with the new Z value demonstrates that the value written was incorrect.

Abstract: A speech signal is input to an excitation signal generating section, a prediction filter and a prediction parameter calculator. The prediction parameter calculator calculates a predetermined number of prediction parameters (LPC parameter or reflection coefficient) by an autocorrelation method or covariance method, and supplies the acquired prediction parameters to a prediction parameter coder. The codes of the prediction parameters are sent to a decoder and a multiplexer. The decoder sends decoded values of the codes of the prediction parameters to the prediction filter and the excitation signal generating section. The prediction filter calculates a prediction residual signal, which is the difference between the input speech signal and the decoded prediction parameter, and sends it to the excitation signal generating section.

Abstract: A method and system for determining the bit patterns to be loaded into control registers of a specific electronic integrated circuit, including a computer software tool which accesses a table of register field bit pattern alternatives that can be loaded into the circuit in order to cause the it to operate in a selected manner. This table also contains English descriptors for each of the field choices so that the user may easily select the desired bit pattern for each field in order. Functional variables for a certain class of integrated circuits, such as those which operate as communications controllers, for example, are individually mapped into various control register fields in order that the computer system designer is led through the specific register choices which must be made so that one particular integrated circuit of this class will carry out the desired functions.

Abstract: Digital samples of an underlying analog audio-frequency signal are converted to transform coefficients and a first bit assignment value indicating the number of quantization levels or bits is adaptively assigned to each coefficient according to the power distribution of the transform coefficients. The transform coefficients are weighted according to a prescribed pattern such as human's auditory sensitivity, and a second bit assignment value is further adaptively assigned to each transform coefficient according to the power distribution of the weighted transform coefficients. One of the first and second bit assignment values is selected according to the power distribution of the transform coefficients and used to quantize the transform coefficients. The quantized transform coefficients are multiplexed with supplemental information derived from the transform coefficients for transmission to a receiving site.

Abstract: An image memory management system for tiled images. The system defines an address space for a virtual memory that includes an image data cache and a disk. An image stack for each source image is stored as a full resolution image and a set of lower-resolution subimages. Each tile of an image may exist in one or more of five different states as follows: uncompressed and resident in the image data cache, compressed and resident in the image data cache, uncompressed and resident on disk, compressed and resident on disk and not loaded but re-creatable using data from higher-resolution image tiles.

Abstract: A programmable interrupt controller having a plurality of interrupt request inquest inputs and an interrupt request output for connection to a central processing unit (CPU) includes means for interrupting the CPU over the interrupt request output responsive to an interrupt request from any one of the interrupt request inputs and a priority resolver for assigning a priority position to each of the interrupt request inputs to create an interrupt priority hierarchy. The interrupt controller is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

Abstract: An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.

Abstract: A video processor, having an image data bus across which image data can be transmitted, is provided. The video processor includes a memory section for storing image data transmitted thereto, the memory section being coupled with the image bus. The video processor further includes first and second buffering devices respectively coupled with the image bus. The first buffering device is capable of buffering image data transmitted from the input device to the storing means, while the second buffering device is capable of buffering image data transmitted from the memory section to the output device. Each of the first and second buffering devices is adapted to generate a request signal when seeking access to the image bus.

Abstract: The cross-link register allows multiple digital processors to pass data and control parameters to a common region. The N-port wide bandwidth crosslink register (WBCR) represents a method for interconnection of N different digital interconnection units (DIUs). The WBCR comprises a group of registers, multiplexers, and a clock circuit, in which: (1) each DIU has write access to only one register which is dedicated to it; (2) each DIU has guaranteed read access to the dedicated registers of any other DIU; and (3) all DIUs may be run asynchronously. The output of each register is routed to the input of each multiplexer. The address lines of each port allow the selection of the output of the particular register, including the register associated with the calling port (for example, port 1 can access all registers, including register 1). The clock establishes the refresh interval of the registers, which are assumed to be collections of master-slave data flip-flops.

Abstract: A voice recognition system includes a microphone for converting a voice to an electrical voice signal including voice and non-voice sound portions. An acoustic processing unit detects power and spectrum of the electrical voice signal, and outputs power time-series data and spectrum time series data. A voice section detection unit uses the power time-series data to detect a start point and an end point of the voice sound portion, and outputs an end decision signal indicative of such end point. A word dictionary stores word labels ordered in accordance with frequency of use, as well as word numbers and word templates. A recognition unit receives the feature time-series data and calculates a degree of similarity between the voice and the word templates. A sorting unit sorts data calculated in the recognition unit in accordance with the degree of similarity.

Abstract: A virtual machine system includes a storage for storing at least transfer priorities of virtual machines, a queuing part for making a queue of data transfer requests which request data transfers between a main storage and an external storage and are received from operating systems which operate on each of the virtual machines, a limiting part for limiting a transfer data length of one data transfer which is requested by each data transfer request in the queue of the queuing part depending on the transfer priority of the virtual machine from which the data transfer request is received, so that a data transfer is made in divisions if the requested transfer data length exceeds a length limit determined by the transfer priority, a generating part for generating a first data transfer request in place of each operating system with the transfer data length determined by the limiting part so as to start a first data transfer between the main and external storages, and a calculating part for calculating a data length

Abstract: A graphical programming system with a spreadsheet base for enabling users to create graphical programs for displaying and manipulating data. The system architecture supports direct entry of information into cells and cell extension to display all information entered into a cell in one view. The architecture further supports modified formulas known as actions that execute only after being independently initiated by a user or another process. Conditional functions known as "watchers" are also provided. Watchers contain procedures to perform and permit a program created with the system to monitor data and respond to it. For ease of understanding, information within cells may be represented graphically by objects such as buttons and meters. The objects may be user-designed or provided by the programming system. They are selected via pop-up menus and list windows within the system's user interface.

Abstract: Before an optical disk is inserted into an electronic filing system, one of three mode-setting keys provided on a keyboard is pushed, thereby setting an automatic mode for permitting automatic updating of retrieval data items, an inhibit mode for inhibiting the automatic updating of retrieval data items, and a select mode for selecting the automatic updating of retrieval data items or the inhibition thereof. The mode, thus set, is recorded on a magnetic disk. When the optical disk is inserted into the system, the mode is read from the magnetic disk. The mode read from the magnetic disk controls the updating of the retrieval data items recorded on the magnetic disk.