Abstract: A method and apparatus for natural language processing using morphology and rhyming. The method and apparatus employ a hybrid of dictionary and rule-based approaches for both speech and speech recognition. In an illustrative embodiment of the present invention the pronunciation of a word is determined by rhyming the word, or components of the word, with a reference word, or components of the reference word. In another illustrative embodiment of the present invention, the spelling of a word is determined by rhyming the word, or components of the word, with a reference word, or components of the reference word.

Abstract: A communication system containing a plurality of node elements. Each node element contains: a main communication unit containing a multiplexer/demultiplexer unit, a management control unit, a data input/output terminal unit, a switch unit, a connection mode control unit, and a link establishing unit. The connection mode control unit connects the data input/output terminal unit to either the management control unit in its own node element or another management control unit in another remote node element, by controlling the switch unit. The link establishing unit establishes a link for the data input/output terminal unit to access the management control unit in another remote node element through an overhead channel between the node elements.

Abstract: A priority selector of a system including a plurality of processors and a shared source commonly used by the processors sets a priority of requests supplied from the processors for using the shared source and supplies a use permission to a single processor. The priority selector has a plurality of lock request priority setting circuits corresponding to the processors and a request selector. When a contention occurs between an own request from a processor and other request from another processor, the corresponding lock request priority setting circuit upgrades the non-permitted own request as a high priority request when the other request is permitted, and downgrades a following own request as a low priority request when the own request is accepted.

Abstract: A method and apparatus for determining the location of an entity using an alias (or entity name) in a communication system. A second node or entity transmits a first signal to a first router connected to a first local network of the communication system including the alias, wherein the alias includes a zone name. The first router forwards a second signal including the entity name from the first signal to other routers in the network until a second router connected to nodes having the zone name in the entity name is located. Each second router translates the second signal into a third signal which includes the alias, and using a first zone multicast address, multicasts the third signal to a first set of nodes. Each node of the first set of nodes determines whether the zone name contained within the alias is equal to a zone identifier for each node of the first set of nodes. Each node having the zone name determines whether the alias contained within the third signal is equal to alias information for the node.

Abstract: A two-way data transfer device for the data interface between two data-exchanging cells including a data source and a data sink with at least one buffer provided in each cell. When the transmitter buffer is full or the receiver buffer is empty, a backward cell stop signal freezes the state of the data source or the data sink and the cell stop signals are controlled by status signals from the respective buffers.

Abstract: A hardware-based system for managing multiple input/output devices sharing the same set of addresses in a computer system is described. The new VIRTUAL ENABLED state is a hybrid of the current ENABLED or ACTIVE and DISABLED or INACTIVE states. In the ENABLED state, an input/output (I/O) adapter responds to I/O addressing and presents interrupts to the processor. In the DISABLED state, the I/O adapter does not respond to I/O addressing and does not present interrupts. In the new VIRTUAL ENABLED state, the adapter does not respond to I/O addressing (as in the DISABLED state), but will still produce an interrupt (as in the ENABLED state). With the VIRTUAL state, multiple I/O adapters that would normally content for the same set of addresses (ENABLED state), or optionally be rendered inoperable (DISABLED state), can always remain available for I/O. A single register where the processor can read the interrupt status for all ENABLED and/or VIRTUAL ENABLED adapters sharing the same set of addresses is provided.

Abstract: For controlling an original interruption request produced in each of peripheral units (12-1 to 12-N), the peripheral units are connected to an interruption control line (20) in common. When the original interruption request is produced, the peripheral unit in question continuously supplies an interruption control signal to the interruption control line unless the interruption control line is already supplied with the interruption control signal from other peripheral units. A timer circuit (23) of the peripheral unit in question times a preselected time interval from a time instant at which the peripheral unit in question begins to supply the interruption control signal to the interruption control line. The timer circuit suspends its operation while an interruption request line (10) is supplied with an interruption request signal from other peripheral units. When the time interval is timed, the peripheral unit in question continuously supplies the interruption request signal to the interruption request line.

Abstract: A speed governor for a microprocessor which prevents the operation above a selected frequency. Three resistors in a bridge network are switched capacitor "resistors" controlled by the input clocking signal. The value of the fourth resistor of the bridge is selected through connections to bonding pads. The bridge through a comparator disrupts the microprocessor's operation. The bondings also permit selection of an oscillator range and phase gap in the internal clocking signals.

Abstract: When image information is to be transferred between processing units having different image information forms, e.g., the pixel width and plane width of image information, the image information is converted by a reformatting unit using the form attribute information of a transfer source and that of a transfer destination. With this operation, a long processing time is not required to transfer image information between arbitrary processing units having different image information forms, e.g., the pixel width and plane width of image information, and there is no need to impose limitations on the types of forms which can be processed on one apparatus, thus enabling high-speed processing and realizing a flexible system.

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation.

Abstract: A satellite wide area communications network (10) includes a remote transmitter/receiver (28A) that is coupled through a modem unit (30A) to multiple card readers (12A-1 to 12A-n). A master transmitter/receiver (26) is satellite linked to the remote transmitter/receiver and is coupled through a central packet network (16) to multiple host computers (18-1 to 18-j). A network host computer address is determined for each transaction card inserted in the card readers, and the network address is processed to establish a direct link to the host computer for the card through the modem unit, the satellite link (22A, 20, 24), and the central packet network.

Abstract: An automatic organization of images in computer memory is provided as a doubly-linked (or multiply-linked) list data structure which reflects in its interconnections to relationships between various stages in complex image processing tasks. Data structures, implemented in an appropriate high-level computer language such as C, contain pertinent information about the image as well as pointers (memory addresses) to other data structures and their associated images. These pointers allow the construction and maintenance of the linked list relationships between images. Since the relationships between images in the linked lists are equivalent to the relationships between stages of image processing tasks, the complex tasks of image processing are automatically documented in the linked list data structure without the necessity of maintaining an auxiliary written record.

Abstract: A level measuring circuit first measures a level of an input speech signal. Next, a coefficient calculating circuit determines a value for suppressing a change of the level of the input speech signal on the basis of an output of the level measuring circuit. Then an input speech signal delay circuit delays the input speech signal by a time required for processing in the level measuring circuit and the coefficient calculating circuit. Finally a multiplying circuit multiplies an output of the input speech signal delay circuit by an output of the coefficient calculating circuit to obtain an output speech signal in which changes in level of the input speech signal are suppressed.

Abstract: A system and method for interpreting messages sent from an I/O device to an application object in an object-oriented environment, such that the messages interpretation of these messages will be consistent regardless of the I/O device used to generate them. Dynamic binding is used to interpret any object-object interactions that may occur. In general, the message interpretation abilities of the present invention allows additional I/O devices to be used with the object-oriented environment without having to update all the application objects in the environment.

Abstract: Disclosed is a multifunction cogenerator or graphics processor for use in a graphics rendering processor. The graphics processor comprises dual graphics engines operating in parallel, with one of the engines having higher operating priority than the other. The graphics processor comprises a conics, vector, and area fill generator, a symbol generator, a bit block transfer operator, and a block texturing and complex clip mask processor synchronously controlled by a multiprocess scheduler. Included in the graphics processor is a large display memory for receiving and storing program instructions and data generated by an external host processor, internal generators and processors, and a bit mapped memory of a graphics display. The graphics processor provides hardware specific graphics functions and externally programmable general purpose processing.

Abstract: The arithmetic processor of a digital computer system has means for performing, on its output operands while they are in transit to memory for storage, such manipulations as operand alignment, conversions between packed and zoned format, insertion of signs, and insertion of predetermined characters for edit functions. Two registers are provided, each having a capacity equal to that of a memory word. Each register is provided with segmented input selection means for selecting from among calculation results, residual data retained from operand fetching, signs, and constants. The two registers are OR'd together to produce desired words for storage in the system's memory.

Abstract: An image filing system has first and second image storage devices and a retrieval data storage device. Image data representing a plurality of images are stored in the first image storage device, and retrieval data corresponding to the image data are stored in the retrieval data storage device. Desired image data are specified according to the corresponding retrieval data, and retrieved from the first image storage device and outputted to the second erasable random-access image storage device. Link information which indicates other image data related to the specified image data is added to the retrieval data. When desired image data are specified according to the corresponding retrieval data and retrieved and outputted to the second image storage device, the other image data related to the desired identified image data can quickly and efficiently be retrieved according to the link information.

Abstract: A circuit has a multiple port memory and a plurality of processor elements having write and/or read addresses connected to addresses of the multiple port memory. A register, a delay circuit and/or a buffer memory may be formed among the processor elements in dependence on the connections of the write and read addresses.

Abstract: Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i.e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.

Abstract: An improved printing machine, of the type in which image data, addresses and control data can be substantially concurrently transferred across multiple multipurpose buses, is provided. The printing machine comprises a first multipurpose bus adapted to substantially concurrently transfer a first set of the image data, addresses and control data and a second multipurpose bus adapted to substantially concurrently transfer a second set of the image data, addresses and control data. A module for processing the first and second sets of data communicates with the first and second multipurpose buses while a first discrete input/output module communicates with the first bus. Both the first processing module and the first discrete input/output module are adapted to transfer the first set of data between one another. A second discrete input/output module communicates with the second multipurpose bus and a third discrete input/output module communicates with the second multipurpose bus.