Abstract: A video image storage, processing, and distribution system is provided with a processing and a distribution subsystem. The processing subsystem comprises at least one high performance video signal input device, one recording format independent hierarchy of storage, at least one recording format and resolution independent video data processor, and a high performance digital data recorder. The distribution subsystem comprises an archive library of recording format independent high performance digital tapes and instrument data players, a recording format independent hierarchy of staging storage, at least one recording format independent video distribution control processor, and a RF signal generation subsystem. The hierarchical storage of the processing subsystem comprises a first level of high performance random access mass storage amenable to large volume storage and high performance file transfers, and a second level of high performance random access storage amenable to high performance byte manipulations.

Abstract: A method of passing data between objects located distributed among a plurality of virtual address space domains established by processes executing on a data processing system comprises several steps. First, a session initiation message from a source object in a domain is broadcast to other objects in the domain. Responsive to receipt of the session initiation message by a domain agent (a type of object) for the domain, forwarding the session initiation message from the domain agent to each of a plurality of domain agents in other virtual address space domains. Responsive to receipt of the session initiation message by the domain agent for a second domain, transmitting the session initiation message from the domain agent for the second domain to an agent object in the second domain for the source object.

Abstract: A method and apparatus for transferring packets of information with different attributes from a device interface to buffers in a host memory dedicated to particular attribute values or ranges of values. The apparatus consists of multiple shared data structures in the form of receive rings, each associated with memory buffers dedicated to a particular range of values for a particular packet attribute. The device interface determines which receive ring is associated with a buffer dedicated to the proper attribute value range by comparing the value of the attribute of the received packet with the values of attributes associated with the buffers of each ring. A sequencing ring is provided to store the order in which each receive ring must be accessed by the host cpu when retrieving packets. This sequencing ring ensures that the host cpu will retrieve the packets in the order in which they were received.

Abstract: A broadcast digital sound processing system includes an ISA (Industry Standard Architecture) bus compatible personal computer with a hard disk drove and a sound processor board installed in an expansion slot of the computer. The board includes a stereo input, analog to digital converter (ADC) and a stereo set of digital to analog converters (DAC's) interfaced to a digital signal processor (DSP) chip. A stereophonic audio signal is converted to digital data by the ADC and communicated to the computer by the DSP chip through a two port record first-in/first-out (FIFO) buffer for storage on the disk. A program is played back by communicating a program data file through a two port playback FIFO buffer to the DSP and from there to the DAC's for reconstruction to a stereo set of analog signals. The reconstructed audio signals may then be used as a modulating signal for radio broadcasting.

Abstract: The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control means are provided for monitoring the status of each channel and each port in order to achieve expeditious transfers through a selected port between the channel and peripheral devices. Error reporting is limited to the area directly affected by the error, and immediate disconnection helps to isolate the error and allow time for error recovery before the particular channel or port again becomes available.

Abstract: An arrangement whereby a passive line concentrator (100) can be connected in a managed token ring network includes a special concentrator port (200) in an active concentrator (10) which is adapted to have inserted the ring-in port (130) of the passive line concentrator. The special concentrator port of the active concentrator supplies a small phantom current to the passive concentrator, which returns the phantom current only if it has at least one active port. Detection of the returned phantom current controls insertion of the special concentrator port into the network.

Abstract: The invention relates to a multi-chip computersystem with master-slave latches. It is known to provide all latches on all chips with two clock pulses, respectively. With the help of the latches the digital signals are pipelined through the logic gates on the chip. Due to tolerances, the edges which control the masters and the slaves have a skew. According to the invention, one of the two clock pulses is generated on the chip itself, respectively, by ANDing an auxiliary clock pulse with the other of the two clock pulses. This has the result, that the above mentioned edges of the two clock pulses occur almost at the same time with the consequence that the frequency of the clock pulses can be increased.

Abstract: A video processor, for transferring a set of image data from an input device to an output device, is provided. The video processor is intended for use in a printing apparatus having a controller for controlling operation of the input and output devices as well as the video processor, while the video processor has an image bus across which the set of image data can be transmitted. The video processor comprises an integrated adaptive compressor for buffering a preselected number of the bytes, the integrated adaptive compressor communicating with the input device. A memory communicates with the integrated adaptive compressor, the memory being capable of selectively storing the preselected number of bytes. The memory also includes predesignated addresses at which the bytes can be stored, and the controller communicates with the memory. The video processor further comprises a direct memory access arrangement, the direct memory access arrangement communicating with the integrated adaptive compressor and the memory.

Abstract: In a bridge unit for connecting branch LANs through a trunk LAN, of address information registered in an address translation table, address information associated with a station not subjected to message transmission or reception for a predetermined period of time is recognized as address information to be deleted from the address translation table After this recognization, when a message is to be transmitted to a destination station represented by the station address included in the address information to be deleted, message transmission is performed by using the address information to be deleted When a response message is not received from the destination station, the address information to be deleted is deleted from the address translation table, and the message is retransmitted by broadcast.

Abstract: A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.

Abstract: An intelligent power supply system for a portable computer, the computer having a central processing unit (CPU), and being operable in response to power supplied from at least two chargeable batteries or an alternating current (AC) adapter, includes means for detachably coupling the batteries to the computer and a PC-CPU for controlling power supply independent of the CPU. The PC-CPU has means for receiving battery select information for controlling power supply and generating a control signal. The power supply system further includes battery control circuit means, connected to the AC adapter and the batteries, for selecting and controlling the AC adapter or one of the batteries based on the control signal. Accordingly, the proper battery for the usage can be installed in the portable computer operable on battery power, and the computer can be operated continuously on the battery power for a long period of time.

Abstract: An I/O address assigning device in a data processing apparatus having a standard port provided in the main unit for connecting the main unit to an I/O address assigning device so as to increase the function of the data processing apparatus and an I/O connecting portion for connecting an additional board provided with an I/O port therein. The I/O address assigning device comprises a control means for disabling the I/O port in the main unit for operation in order to prevent conflict of the I/O port in the main unit and on an additional board which have the same address, a detecting means for detecting the preset I/O address of the additional I/O port in the state in which the I/O port in the main unit is disabled, and an address assigning means for assigning an I/O address different from the preset address of the additional I/O port which is detected by the detecting means to the I/O port in the main unit.

Abstract: An image processing system provided with a reception device for receiving image information and an output device for outputting image information at high resolution in case where the received image information is binary image information, and for outputting image information at resolution lower than resolution of the received image data in case where the received image information is other than binary image data. Thereby, a quantity of image information can be reduced without degradation of picture quality. Thus an image can be transmitted and stored.

Abstract: A CPU or other graphics processor provides a pixel data stream to a graphics controller over a system bus. The pixel data stream includes a graphics controller address as well as a pixel type tag, which in the presently preferred embodiment comprises 4 bits. In addition to the graphic controller address and pixel type tag, a pixel address and pixel data are provided. The pixel type tag identifies the "type" of pixel data in the data stream supplied to the graphics controller. If the data identified by the pixel type tag corresponds to the type of data which the frame buffer is configured for, then the data provided over the system bus is simply passed through the graphics controller and written at the appropriate pixel address in the frame buffer.

Abstract: Count, key, data (CKD) datas are stored on fixed block (FBA) disk recorders (DASD). A virtual track is created which emulates a physical CKD track such that the byte displacement of each CKD record on the virtual CKD track is the same as the byte displacement would be on a physical CKD track. This enables computer programs using CKD formatted data to record on the FBA recorder in an emulation mode. Each FBA block includes a header outside the addressing of the virtual CKD track which includes a byte displacement pointer to the beginning of a first CKD record stored in the FBA block, if any begins in such FBA block; otherwise the header indicates that no CKD record begins in the block. A last record indicator is included in the count field emula-tion for assisting in finding end of the virtual track.

Abstract: A frame buffer for constructing a full page bit map for a raster device includes a plurality of memory cells arranged in lines and columns. The bits in the memory cells have a predetermined order, and the addresses associated with the memory cells have a linear consecutive sequence when the frame buffer is scanned out according to an originally planned direction. However, when the scan out direction is perpendicular to the originally planned direction, the predetermined bit order and the linear consecutive address sequence will not hold. The frame buffer in the invention includes mechanisms to adjust the bit order and scan out addresses when the scan out direction is perpendicular to the originally planned scan direction.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

Abstract: A host computer, a graphics processor which receives and executes commands generated by the host computer, a display memory for storing display data, and a display device for displaying the display data are provided. A graphics context is also provided in which the parameters of a current image are stored. A processing unit for receiving and executing the graphics commands issued by the host computer and for converting the parameters stored in the graphics context into the display data, and a drawing unit for storing the display data in the display memory are also provided. Furthermore, a shared memory is provided which is directly accessible to the host computer so that it can write the parameters of a next graphics command into the shared memory while the graphics processor is executing a current command. The shared memory is also directly accessible to the graphics processor so that it can receive the parameters of the next graphics command to be executed directly from the shared memory.

Abstract: The tones (or densities) of individual edge pixels of vector data are determined by first dividing each edge pixel into subpixels, after which the thus-determined tones are fed to a laser printer or other output unit. Advantageously, the present invention smooths jagged edges by performing an anti-aliasing process. To achieve this smoothing of graphic data, any of a variety of filters, each having particular weights, are used for the process of dividing edge pixels into subpixels.

Abstract: A digital image processing system comprises a processor at a central, first site; and digital image processing equipment such as an analyze scanner and an expose scanner at a second site remote from the first site. The processor and the digital image processing equipment are connectable and are adapted to pass signals therebetween corresponding to signals generated by the digital image processing equipment. These signals may be representative of operator commands or digital data generated at the second site which can be monitored at the first site.