Abstract: A block texturing and complex clip mask processor for use in a graphics rendering cogenerator. The processor provides two directly accessed texture patterns, and combinational logic for combining texture patterns and graphic primitive signals. The combined texture pattern signals and primitive signals provide for both textured graphic primitives and complex shaped clip mask areas. Also included are inputs for defining rectangular clip masks and logic means for combining the rectangularly clip masks with the texture, graphic primitive and complex clip mask signals.

Abstract: A data processing apparatus is provided for outputting processed data and data input via an input device, such as a mouse. That data is stored in a memory to be transferred for display in a display device. A controller monitors the data transferred to the display device from the memory, and controls, in accordance with the monitoring, the storage of the data in the memory of the processed data and the input data.

Abstract: A system capable of compensating for the shortage of storage capacity by deleting stored picture image datafiles as appropriate from time to time on the basis of such factors as the degree of importance of each file, the lapse of time since the creation of each stored file, and the effective residual storage capacity for the image files.

Abstract: Resets on a data processing system are targeted to specific locations of that processing system and have different effects. Some resets are transparent to instruction execution while other resets will interrupt the normal execution of instructions. In addition, in a multi-zone environment resets in one zone do not automatically propagate to the other zone; instead, each zone generates its own resets.

Abstract: Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced.

Abstract: An image processing system having operating and stand-by modes of operation which are to be selectively put into effect, including a plurality of slave data processors each operative to execute a set of predetermined functions assigned thereto, a master data processor for controlling the operation of each data processor, the master data processor being operative to output a data processing command requesting any of the slave data processors to execute any of the predetermined functions assigned to the slave data processor and a control command predominant over the communication of data dictating the operation of each slave data processor, and an interface bus providing connection between the master data processor and each slave data processor for allowing transmission therethrough of the data processing command and the control command to any of the slave data processors, the master data processor being operative to detect a state in which the master data processor is currently coupled to any one of the slave

Abstract: Devices for the digital recording and reproduction of speech signals are used, for example in answering apparatus. In order to reduce the quantity of data to be stored without noticeably affecting the acoustic quality of the speech, it is proposed to encode speech signals by means of a residual signal speech encoder.

Abstract: Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame buffer. The VRAMs in the frame buffer are addressed with coordinate pixel locations on the display device corresponding to locations of the graphics primitives on the display device. The frame buffer is accessed with a graphics rendered according to arbitrarily shaped tiles containing pixels such that the pixels within the tiles have potentially different VRAM addresses.

Abstract: A breakpoint apparatus incorporated in a single chip microprocessor. The apparatus permits breakpoints on specific references to either program instructions or data. The width of the breakpoint address can be varied, the apparatus includes a logic circuit for determining if the reference represented by the breakpoint address overlaps the current virtual address.

Abstract: A method of configuring a computer system having internal and external Serial Input/Output (SIO) ports, includes determining the designation of each SIO port present in the system as being either primary, secondary, or disabled. The designations of the physically present SIO ports are used to update the contents of a non-volatile memory. Prior to updating the non-volatile memory, a read operation is performed on the non-volatile memory. If the non-volatile memory presently reflects the status of the physically present SIO ports, the updating of the non-volatile memory is bypassed.

Abstract: An improved optical disk data storage system method are disclosed. In an optical disk storage system, a data compression device is interposed between a host computer and an optical disk controller to permit data storage and retrieval operations on an optical disk to occur at a faster rate than would otherwise be possible. Data is compressed when it is received by the optical disk controller and is decompressed before it is sent to the host computer. In this way data may be efficiently stored on an optical disk while providing plug compatibility with a host computer designed to store and retrieve data on a magnetic media data storage device.

Abstract: This invention is an improved method for transmit polling of buffered UARTs. For each polling interval, the method predicts the minimum number of characters needed to keep the transmitter from going idle before the next polling interval and places exactly that many characters in the transmit fifo.

Abstract: The performance of speech coding in the presence of bit errors is improved. The quantized parameter bits are grouped into several categories according to their sensitivity to bit errors. More effective error correction codes are used to encode the most sensitive parameter bits, while less effective error correction codes are used to encode the less sensitive parameter bits. This method improves the efficiency of the error correction and improves the performance if the total bit rate is limited. The perceived quality of coded speech is improved. A smoothed spectral envelope is created in the frequency domain. The ratio between the actual spectral envelope and the smoothed spectral envelope is used to enhance the spectral envelope. This reduces distortion which is contained in the spectral envelope.

Abstract: A vector processor in which input/output of vector data to and from a vector register is effected by a load/store pipeline from a main memory, includes a load pipe for reading data of a plural-byte width from the main memory in one access, a plurality of vector registers for storing data read by the load pipe, each having a plurality of entries of an 8-byte width, mark bit stacks provided one for each of the vector registers and each having at least the same number of entries as those of the vector register, the entries of each mark bit stack storing mark bits for indicating which one of the plural-byte data stored in the entries of the corresponding vector register is valid, and a shifter for sending the valid data to an operation unit in accordance with the mark stored in the mark bit stack.

Abstract: A computer system is disclosed in which different type of communication links are provided between different computers. A high speed data communication link between a personal computer (PC) and a midrange computer is disclosed. An application is run on the midrange computer, and simultaneously a different but related application is run on the PC. Then, the PC initiates a write command to write data from the PC to the midrange computer without prior direction from the midrange computer to initiate the write command. Next, the data is written into a buffer pool memory based on memory resident indicators whereby no channel program is required. This expedites the data transfer. The midrange computer application subsequently reads the data from the buffer pool memory. A master/slave relationship is also provided between the midrange computer and another computer or external device for more controlled data communications.

Abstract: A voice-operated remote control system which transmits a remote control signal in response to a voice command has a degree-of-importance determining unit for determining the degree of importance of the voice command that is applied to the remote control system. The degree-of-importance determining unit sends a degree-of-importance signal corresponding to the degree of importance of the voice command to a recognition accuracy determining unit. Depending on the degree of importance of the input voice command as indicated by the degree-of-importance signal, the recognition accuracy determining unit determines whether the accuracy of the recognition result is high or low, and delivers only the recognition result of higher recognition accuracy to a transmitting circuit.

Abstract: A data processing device includes first and second blocks which have different processing times and which operate in synchronism with a clock signal. One of the first and second blocks is selected and enabled in accordance with an instruction representing which of the first and second blocks should be selected and enabled. A clock change signal is generated on the basis of the instruction. A period of the clock signal is changed in accordance with the clock change signal.

Abstract: A method and apparatus are used to adapt a disk drive accessing system to access a maximum storage capacity of at least one disk drive. A Basic Input/Output System (BIOS) memory extension is carried by an adapter. The disk drive to be accessed is identified and address parameters for the disk drive are determined based on instructions in the BIOS extension. The address parameters correspond to the maximum storage capacity of the disk drive. The address parameters are determined by the disk drive accessing system and are suitable for being used by the accessing system in accessing the maximum storage capacity of the disk drive. The disk drive is then configured for being accessed using the address parameters.

Abstract: A method for allowing direct graphics access to backup storage areas in frame buffer memory used for retained windows and controlled by a graphics accelerator which includes the steps of establishing a shared memory file in system memory for the backup storage area indicating that the retained windows area initially exists in excess frame buffer memory, the shared memory file having storage to indicate the use of the shared area by a process; generating a page fault whenever access to the graphics accelerator is attempted and the state of another process is stored on the graphics accelerator; and calling a device driver in response to the page fault to switch the context stored on the graphics accelerator to that of the process attempting the access.

Abstract: A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.