Patents Examined by Dan Fiul
  • Patent number: 6230116
    Abstract: A computer system including computer resources, an operating system operative to control said computer resources; and a 3D interface enabling a user to interact with the operating system and operative to provide a plurality of display representations of at least a portion of the computer resources from a corresponding plurality of different viewpoints.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: May 8, 2001
    Assignee: Clockwise Technologies Ltd.
    Inventors: Nir Ronen, Ron Amihai
  • Patent number: 6212492
    Abstract: A simulation method of performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit, on the basis of a positional relationship between transistors, well contact interconnections, and sub-contact interconnections of the layout data. Parasitic resistances and parasitic capacitances in conductive regions between sub-terminals of the transistors are evaluated. A simulation apparatus for performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit is also disclosed.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: April 3, 2001
    Assignee: NEC Corporation
    Inventor: Hiroyoshi Kuge
  • Patent number: 6173244
    Abstract: A test system in a communication system provides for a simulation of a test telephone call to a switching system under test. A test controller is integrated with the system under test for simulating the telephone call to the system under test. A high speed interface card with a processor is interfaced with the computer on the system under test through a computer bus interface for gathering call processing event data, A high speed interface communicates with the test controller to convey the simulated call processing event data to the controller computer.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: January 9, 2001
    Assignee: Lucent Technologies, Inc.
    Inventor: William H. Pyritz
  • Patent number: 6117181
    Abstract: The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit simulations which collective simulate a circuit is represented and controlled by a respective local synchronization thread ("LST") of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation. Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: September 12, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Glenn A. Dearth, Paul M. Whittemore
  • Patent number: 6117179
    Abstract: An electrical rule check program takes simulation output files as input and performs an electrical rule check on the simulation to determine if any electrical design rules have been violated. The program scans a simulation output file to produce a subcircuit name list, an instance name list, and an internal index list for each subcircuit. If the number of circuit nodes is less than a first predetermined value, a window limit is set to equal the number of nodes times the number of data points. If the number of nodes is greater than the first predetermined value and less than a second predetermined value, then the window limit is set to equal some first predetermined fraction of the product of the number of nodes and the number of data points.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: September 12, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexius H. Tan, Shane Hollmer, Jonathan Su
  • Patent number: 6110217
    Abstract: A multiprocessor system and method are provided for simulating electrical circuits. The circuit is divided into portions, and separate simulator modules perform a multi-rate behavior simulation, to simulate the performance of respective circuit portions. The simulator modules communicate using block waveform relaxation. Accordingly, the amount of inter-process communication is advantageously low, and the need for backing up digital simulation processes is avoided, providing advantageously fast performance. A system according to the invention is preferably implemented, either physically or logically, in a simulation backplane configuration, having a common connective bus structure, to which multiple active simulation modules are coupled through an interface which is standardized for facilitating block waveform relaxation.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: Tomasz Kazmierski, Timothy Michael Kemp
  • Patent number: 6108494
    Abstract: An optimization mechanism for increasing runtime performance in a co-/ multi-simulation environment by reducing the number of connections between simulators is provided. A simulation backplane includes netlist optimization logic that analyzes the netlists of design partitions and employs a set of rules to reduce the number of connections among simulators participating in a simulation session. According to one aspect of the present invention, synchronizations among a first solver and one or more other solvers that are simulating a design of a system or a portion thereof are limited to situations in which simulation being performed by each of the one or more other solvers is dependent upon event information from the first solver. Partitioned design source information is received for each a plurality of solvers. Based upon the partitioned design source information, partition dependency information is generated.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: August 22, 2000
    Assignee: Mentor Graphics Corporation
    Inventors: Karl Eisenhofer, Arun T. Venkatachar, Kevin Nazareth, Peter Odryna, Robert Michael Bradley
  • Patent number: 6099574
    Abstract: Process simulation for LSIs and other semiconductor devices will handle plural same impurities introduced in different processes as different impurities. Thus, by handling them as different impurities in calculation, it is possible to obtain the distribution profiles of impurities in semiconductor devices without being effected by another same impurity introduced in another process or a number of processes during processing. With this, even a plurality of process conditions are discussed or when one or some of process(es) in a sequence of semiconductor device fabrication processes is (are) changed in procedure, it is not necessary to repeat the process simulation many times from the beginning. And it is possible to easily decide which process must be changed in conditions based on a finally obtained structure of semiconductor devices.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: August 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sanae Fukuda, Hirotaka Amakawa, Takahisa Kanemura
  • Patent number: 6088522
    Abstract: A computer-implemented modeling tool for cellular telephone systems predicts signal strength under real conditions within a building, by considering the effects of inter-building and intra-building structures on transmitted signals. The modeling tool gives more accurate predictions under line of sight conditions, when obstructions occur due to inter-building and intra-building structures.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: July 11, 2000
    Assignee: AirTouch Communications, Inc.
    Inventors: William Chien-Yeh Lee, Jau Young Lee
  • Patent number: 6072948
    Abstract: A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: June 6, 2000
    Assignees: Mitsubishi Electric System LSI Design Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuo Saitoh, Yuuji Okazaki, Mitsunori Matsunaga, Toshinori Inoshita
  • Patent number: 6063127
    Abstract: A method of adaptive sampling for accurate computer model building. The present invention is used in conjunction with a computer system to build models of responses, functions, and the like, that produce a given output for a given input(s). One embodiment in accordance with the present invention includes a computer system, software instructions, and a function to be modeled. The present embodiment directs the computer system to generate a set of equidistant data points for the function based on an input value. The present embodiment directs the computer to use a modeling curve to generate a set of prediction data points based on the odd positioned data points of the equidistant data points. The present embodiment directs the computer to determine whether the locations of the predicted data points satisfy a predetermined convergence criterion with respect to the determined locations of the even positioned data points of the equidistant data points.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: May 16, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: David H. Ziger
  • Patent number: 6058252
    Abstract: A computer system and computer implemented method for deriving constraints with which to direct automatic integrated circuit layout is disclosed. The present invention is particularly adapted for use in the design of large integrated circuits with complex synchronous timing behavior. Preferably, the invented computer system includes means for storing a netlist data structure within a storage means is provided, the netlist data structure representing a circuit configuration having a plurality of circuit elements and representing static timing information for the circuit configuration; means for selecting specified circuit elements to be used for generating the layout constraints, whereby the specified circuit elements that are selected are fewer than, i.e.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: May 2, 2000
    Assignee: Synopsys, Inc.
    Inventors: Mark D. Noll, Kenneth E. Scott, Robert L. Walker
  • Patent number: 6049660
    Abstract: A simulation method for simulating in a lithographic process is disclosed, and the method can expect a size of a resist pattern by obtaining a diffused aerial image model(DAIM) by determining a simplified model in a aerial image to represent a resist process without simulating full processes including a resist process, and then applying the DAIM to a threshold model.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: April 11, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chang Nam Ahn, Hee Bom Kim
  • Patent number: 6049661
    Abstract: A method of simulating the shape of a sample after a surface reaction processing in a short calculation time, where a partial pressure P.sub.S of the reaction gas used for a surface reaction at the surface of the sample is calculated from an equation P.sub.S =P.sub.0 -R.times.J by using the partial pressure P.sub.0 of the reaction gas in the gas feed unit used for the surface reaction, a transport resistance R of the reaction gas in a chamber for performing the surface reaction, and a magnitude J of the flow of the reaction gas numerically found at the time of simulation and this P.sub.S is taken into account in the simulation to calculate the shape of the sample after the surface reaction processing.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: April 11, 2000
    Assignee: Sony Corporation
    Inventor: Koichi Hayakawa
  • Patent number: 6049663
    Abstract: A computer program product has a facility for uninstalling itself. The facility is both efficient and dynamic. The facility only backs up a minimal set of files that may be affected by an installation of the computer program product. The facility dynamically adapts to different possible installations so as to only store backup copies for the particular installation that is to be used. The facility leverages a number of installation files to determine what files to back up.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: April 11, 2000
    Assignee: Microsoft Corporation
    Inventors: Seetharaman Harikrishnan, Jeffrey T. Parsons, Felix Andrew, Christopher J. Guzak
  • Patent number: 6044213
    Abstract: The present invention provides a method of simulating a process for oxidation of silicon. The method comprises the following steps. A time "t" of oxidation calculation is set at zero. An effective surface oxidant concentration of a silicon surface exposed to an oxygen atmosphere is calculated assuming that a spontaneous silicon oxide film as an initial silicon oxide film extends over the silicon surface. The time "t" of oxidation calculation is forwarded by a predetermined time increment .DELTA.t. An oxidation rate is calculated by use of one of the effective surface oxidant concentration and the surface oxidant concentration. A new silicon surface is formed based upon the calculated oxidation rate and the time increment .DELTA.t. Variations in thickness of the silicon oxide film over time are found by a deformation calculation.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: March 28, 2000
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 6041171
    Abstract: A method and apparatus for modeling material handling systems for carrying discrete objects is disclosed which is capable of displaying models of a system in two, three, or four dimensions. The system is based on an existing program for modeling fluid flow networks, such as the piping design module of the CATIA CCPlant design package. All of the changes to pipe design program are made using tools present in that program, and no computer code needs to be modified.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 21, 2000
    Assignee: Jervis B. Webb Company
    Inventors: Dennis R. Blaisdell, Bruce W. Mattison, Robert C. Farthing, Michelle A. Sarosy
  • Patent number: 6035115
    Abstract: A method for performing simulation of a semiconductor integrated circuit is disclosed in which a circuit simulation result taking into consideration can be obtained relative variation. In the method, possible maximum and minimum values of an element parameter, i.e., element parameters of a worst case taking into consideration the relative variation is determined from prescribed absolute and relative variation ranges to form a variation model. Based on the variation model, worst-case simulation is carried out taking into account the relative variation.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventor: Kyou Suzuki
  • Patent number: 6035279
    Abstract: In a method and apparatus for awarding a prize in a commercial establishment which includes at least one data terminal for communicating over at least one data line with a central processing unit, the communicating of the at least one data terminal including a data stream of information representing a commercial transaction performed at the data terminal, the improvements are:a) detecting the data stream;b) extracting signals identifying the commercial transaction performed at the at least one terminal from the detected data stream;c) comparing the identifying signals with predetermined reference signals and generating an enabling signal when a predetermined relationship exists between the reference and identifying signals; andd) generating a win signal upon receipt of the enabling signal; and, for awarding a prize based on the win signal.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: March 7, 2000
    Assignee: Markidea S.R.L.
    Inventors: Enrico Montangero, Stefano Reato
  • Patent number: 6028995
    Abstract: A logic-cell model accounts for nonlinear effects in determining propagation delay, thereby providing improved accuracy as compared to existing models, particularly when rise/fall times exceed several nanoseconds. Given a logic cell of the type wherein delay is a function of rise/fall time (TRL) and load capacitance (CL), the method involves choosing a plurality of discrete simulation points associated with the delay, each point also being a function of TRF and CL, after which the delay is determined in accordance with the chosen simulation points. One or more of the simulation points are preferably chosen in conjunction with both the linear and nonlinear regions of the TRL/CL space to ensure accuracy for a wide range of TRL and/or CL values. In the event of an identifiable or discontinuous transition between the linear and nonlinear regions, a discrete simulation point is also chosen with respect to the transition area.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: February 22, 2000
    Assignee: LSI Logic Corporation
    Inventors: Mark W. Jetton, Anura P. Jayasumana