Patents Examined by Dan Fiul
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Patent number: 6028995Abstract: A logic-cell model accounts for nonlinear effects in determining propagation delay, thereby providing improved accuracy as compared to existing models, particularly when rise/fall times exceed several nanoseconds. Given a logic cell of the type wherein delay is a function of rise/fall time (TRL) and load capacitance (CL), the method involves choosing a plurality of discrete simulation points associated with the delay, each point also being a function of TRF and CL, after which the delay is determined in accordance with the chosen simulation points. One or more of the simulation points are preferably chosen in conjunction with both the linear and nonlinear regions of the TRL/CL space to ensure accuracy for a wide range of TRL and/or CL values. In the event of an identifiable or discontinuous transition between the linear and nonlinear regions, a discrete simulation point is also chosen with respect to the transition area.Type: GrantFiled: March 31, 1998Date of Patent: February 22, 2000Assignee: LSI Logic CorporationInventors: Mark W. Jetton, Anura P. Jayasumana
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Patent number: 6026227Abstract: A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces.Type: GrantFiled: September 24, 1997Date of Patent: February 15, 2000Assignee: Atmel CorporationInventors: Frederick C. Furtek, Martin T. Mason, Robert B. Luking
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Patent number: 6018626Abstract: An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..Type: GrantFiled: August 26, 1997Date of Patent: January 25, 2000Assignee: Cirrus Logic, Inc.Inventor: Christopher P. Zook
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Patent number: 6018624Abstract: One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.Type: GrantFiled: January 15, 1999Date of Patent: January 25, 2000Assignee: Xilinx, Inc.Inventor: Glenn A. Baxter
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Patent number: 6016389Abstract: An apparatus and method of evaluating lighting for a given target area that will have an event which is televised. The method includes calculating television foot-candle and vertical foot-candle for various points on the target area as well as calculating the ratio between those two readings. These calculated readings can then be evaluated for the purpose of determining whether sufficient uniformity and intensity exists for given aiming locations on the target area to provide high quality television filming. The apparatus is preferably a computer program that is installed on a computer that would allow both simulations of not yet existing lighting systems to design lighting systems for optimum television coverage or evaluate existing lighting systems to change them for better performance for televising.Type: GrantFiled: May 8, 1997Date of Patent: January 18, 2000Assignee: Musco CorporationInventors: Joe P. Crookham, William E. Brackett, Mark A. DeJong, David L. Barker
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Patent number: 6014511Abstract: A method and system of transparently supporting functionalities on different versions of an operating system (O/S). An application is provided that determines if an O/S executing on a processor provides an O/S service layer. If the O/S service layer is provided, the application loads the O/S service layer. If no O/S service layer is provided, the O/S loads an alternative service layer which emulates a subset of the service provided by the O/S service layer. Regardless of the service layer loaded, the application follows the same flow path after the service layer is loaded.Type: GrantFiled: August 29, 1997Date of Patent: January 11, 2000Assignee: Intel CorporationInventors: Ramamurthy Krithivas, Steven McGowan, Sharma Upadhyayula
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Patent number: 6014509Abstract: A field programmable gate array (FPGA) comprising a matrix of programmable logic cells, a bus network of local and express bus lines, and a system of perimeter I/O pads is disclosed. Logic cells are directly connected to neighboring nearest cells, including diagonally and orthogonally adjacent cells, and are also connected to local bus lines. Such direct cell-to-cell connections allow both directions of signal propagation. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, I/O pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.Type: GrantFiled: September 24, 1997Date of Patent: January 11, 2000Assignee: Atmel CorporationInventors: Frederick C. Furtek, Martin T. Mason, Robert B. Luking
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Patent number: 6011914Abstract: A method for simulating the deformation of regions in a semiconductor device due to oxidation. An oxidation calculation triangular mesh is deformed according to an oxidation calculation, and a diffusion calculation triangular mesh simulates the diffusion of impurity materials. Diffusion calculation control volumes are defined to each vertex of the diffusion calculation triangular mesh. The diffusion calculation triangular mesh and the diffusion calculation control volumes are deformed according to the deformation of the oxidation calculation triangular mesh. Impurity material concentrations are altered according to volume ratio of the diffusion calculation control volume after deformation to the diffusion calculation control volume before deformation. A new diffusion calculation triangular mesh and corresponding new diffusion calculation control volumes are defined for deformed shapes of regions that guarantee Delaunay partitioning.Type: GrantFiled: September 18, 1997Date of Patent: January 4, 2000Assignee: NEC CorporationInventor: Yutaka Akiyama
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Patent number: 6009249Abstract: A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist. While constructing the netlist, instances are checked for directives. The directives indicate that the instance should be tracked as a load circuit. For the instances having such a directive, their nets are flagged and the hierarchal portion of the circuit attached to the flagged nets is flattened. The resulting flat circuit replaces the instance in the netlist as a load circuit.Type: GrantFiled: June 13, 1997Date of Patent: December 28, 1999Assignee: Micron Technology, Inc.Inventor: Larren Gene Weber
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Patent number: 6009261Abstract: Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture.Type: GrantFiled: December 16, 1997Date of Patent: December 28, 1999Assignee: International Business Machines CorporationInventors: Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott
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Patent number: 6004021Abstract: The Toy System is a toy for use with a computer having a display. The system includes a plurality of interconnecting hardware toy pieces and a toy design system software for operating the computer. An inventory database stores an inventory of the toy pieces. An inventory database manager module updates the inventory database in response to player input. A design layout module creates and modifies a toy layout in response to player input using software representations corresponding to the inventory of the toy pieces and conforming to a plurality of design rules, and generates a screen indicating the toy layout. A layout database stores the toy layout created by the player using the toy design system. Other features includes inventory management and control allowing a layout based on a fixed inventory, a layout completion module, a layout library module, a design assistance module, a simulation module and an education module.Type: GrantFiled: September 24, 1996Date of Patent: December 21, 1999Assignee: Chaos, L.L.C.Inventor: James N. Rothbarth
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Patent number: 6002862Abstract: A process and an apparatus which allows, while an input focus is located in a first input area on a display screen, an input of information through a second input area on the display screen. First, it is determined whether or not there is a key input from a keyboard, where the key input is predefined for inputting information through the second input area, and is not predefined for inputting information through the first input area, while the input focus is located in the first input area. When it is determined that there is the above key input, the information designated by the key input, is input through the second input area, while maintaining the location of the input focus in the first input area.Type: GrantFiled: October 6, 1995Date of Patent: December 14, 1999Assignee: Fujitsu LimitedInventor: Shinichi Takaike
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Patent number: 6002863Abstract: A computer implemented method and system for simulating strategic planning and operations uses an operations control language (OCL) which has the characteristics of: (a) a target expression, (b) a condition expression, (c) an integer hierarchical priority level, (d) at least one penalty expression, and (e) a value expression. The OCL is a high level programming language for describing operating policies for simulation models, such as those used in water resources management. The OCL of the invention is written into a simple text file. The OCL has syntax, keywords and Boolean and arithmetic operators.Type: GrantFiled: March 24, 1998Date of Patent: December 14, 1999Assignee: Water Resources Management, Inc.Inventors: Daniel P. Sheer, Anthony Paul Pulokas, Dean James Randall
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Patent number: 5999724Abstract: A simulation system in a work flow control system confirms whether or not prepared business process defining information is valid. The simulation system receives as an input thereto a false case including a name of a document, an attribute name belonging to the document, and attribute values to be selected; virtually moves the false case from a node to another node according to the business process defining information, simulates a process conducted in each node, and generates a journal of these processes.Type: GrantFiled: February 25, 1999Date of Patent: December 7, 1999Assignee: Hitachi, Ltd.Inventors: Mototsugu Iwasa, Hiromasa Nemoto, Hirofumi Kondoh, Hirotoshi Ise
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Patent number: 5999723Abstract: A computer-implemented method for executing a computer file in a CPU emulator (154) to detect a computer virus. The method includes simulating (302) the execution of a predetermined number of instructions of the computer file in the CPU emulator (154), suspending (303) the execution, constructing (304) a state record, temporarily storing (305) the state record in memory, comparing (306) the constructed state record to state records stored in a state cache (158), and indicating (308) that the file is virus free when the constructed state record matches one of the stored state records.Type: GrantFiled: December 1, 1998Date of Patent: December 7, 1999Assignee: Symantec CorporationInventor: Carey S. Nachenberg
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Patent number: 5995729Abstract: In response to a variety of commands entered via a terminal unit, a configuration-management aiding apparatus directly connected to a computer system carries out various kinds of work such as laying-out of pieces of equipment, inspection of the layout of the pieces of equipment for an overlap, inspection of amounts of dissipated heat, inspection of amounts of consumed electrical power, inspection of connection of cables, creation of a cabling work specification manual, creation of a logical-configuration drawing and creation of configuration defining parameters. The configuration defining parameters are transferred to a file in the computer system. The terminal unit of the configuration-management aiding apparatus also functions as a console of the computer system.Type: GrantFiled: May 8, 1998Date of Patent: November 30, 1999Assignee: Hitachi, Ltd.Inventors: Toshio Hirosawa, Tsutomu Ito, Motohide Kokunishi, Atsushi Ueoka, Seiji Inoue, Yoshio Ukai
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Patent number: 5995743Abstract: A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory of a next guest instruction to be emulated, and an indication of a particular native instruction are stored. After an interrupt handler is executed, emulation is resumed by executing native instructions beginning with the particular native instruction. In response to execution of a native instruction of a first type before execution of a native instruction of a second type, the current guest instruction is fetched from memory.Type: GrantFiled: September 22, 1997Date of Patent: November 30, 1999Assignee: International Business Machines CorporationInventors: James Allan Kahle, Soummya Mallick
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Patent number: 5995742Abstract: A method of rapid prototyping a lighting system which is at least one of folded path and multifaceted includes determining output power of the lighting system by calculating phase space density. A method of rapid prototyping a lighting system comprises ray tracing the lighting system, determining photometric quantities which describe the lighting system based on the ray tracing step, and providing a stereoscopic three-dimensional rendering of the lighting system based on the determining step. The three-dimensional renderings reveal any hidden pseudo-image artifacts in a lighting system before the lighting system is actually fabricated. A computer system for rapid prototyping a lighting system comprises a plurality of slave processors networked to a host processor. The slave processor and the master processor cooperate to ray trace the lighting system, and the slave processors perform homogeneous independent tasks.Type: GrantFiled: July 25, 1997Date of Patent: November 30, 1999Assignee: Physical Optics CorporationInventors: Tomasz P. Jannson, Stephen A. Kupiec, Andrew Kostrzewski, Mike Rud, Indra Tengara, Anatoly Vasiliev, Jeongdal Kim
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Patent number: 5991532Abstract: A method that converts multimegabit-rate data into asynchronous transfer mode ATM cells and vice versa which are utilized in a switching system. The method includes determining whether the data is effective or ineffective in accordance with a portion of the data. Converting the data into the ATM cells when the data is determined to be effective. Disregarding the data when the data is determined to be ineffective. The method can be realized by an ATM interface converting unit connected with the switching system and a service interface unit. The service interface unit includes at least one of a switched multimegabit data services interface unit, a frame relay interface unit or a digital signal interface unit.Type: GrantFiled: January 30, 1996Date of Patent: November 23, 1999Assignee: Fujitsu LimitedInventor: Yuichi Harada
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Patent number: 5987242Abstract: A computer system for modeling is disclosed, where the computer system has a storage device, first and second platforms, a portable persistent model, and first and second platform-dependent computerized modeling systems (CMS). Each platform is interfaced to the storage device and provides system-dependent services. The first platform has a first type of operating system and a first type of computer hardware including a first memory, and the second platform has a second type of operating system and a second type of computer hardware including a second memory. The model resides in the storage device in a platform-independent format and includes persistent component objects. The first CMS resides in the first platform memory and the second platform-dependent CMS resides in the second platform memory.Type: GrantFiled: November 10, 1997Date of Patent: November 16, 1999Assignee: Bentley Systems, IncorporatedInventors: Keith Bentley, Samuel Wilson, Earlin Lutz, James Bartlett, John Gooding