Abstract: A multiprocessor computer system that includes an emulation feature for lowest priority processor software compatibility while providing fault tolerance includes first and second processors coupled to a system bus that handles transmission of interruption messages within the system. An instruction resulting in an interruption which specifies an interrupt feature causes microcode to generate a trap. A trap handling routine reads ID information from a register of the first processor, and places it in a target processor ID field of an interruption message which gets broadcast on the system bus. The first processor eventually accepts the interruption message and is designated as the processor in the system which handles the interruption.

Abstract: A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction on one side of the midplane for making connections to the plurality of first printed-circuit boards. The midplane printed-circuit board also has a plurality of second connectors oriented in a second direction orthogonal to the plurality of first connectors on the other side of the midplane. The connectors are positioned such that connection pins on the plurality of first connectors and plurality of second connectors in regions of intersection are double-ended pins common to both. The remaining connection pins of the plurality of first connectors are single-ended connection pins which are connected to the single-ended connection pins of the plurality of second connectors via conductive traces on the midplane printed-circuit board.

Abstract: A simulation system in a work flow control system confirms whether or not prepared business process defining information is valid. The simulation system receives as an input thereto a false case including a name of a document, an attribute name belonging to the document, and attribute values to be selected; virtually moves the false case from a node to another node according to the business process defining information, simulates a process conducted in each node, and generates a journal of these processes.

Abstract: A method and system for assessing quality of service for multimedia traffic under aggregate traffic conditions in a shared transmission network, such as an ATM network. A total number of different traffic services as well as a maximum number of sources for each traffic service are specified by a network operator/designer. Next, for each traffic service a specification of peak rate, average idle sojourn time and an average burst sojourn time are determined, either based upon available standards or calculated based upon models of the traffic services. The total available system bandwidth is specified by a network operator/designer. Finally, the number and size of queues utilized for receiving packetized telecommunication traffic within the network are specified.

Abstract: A performance modeling tool and method permitting the user to define the elements of a distributed system (hosts, networks and response times), and examine the effect on performance of different distributions of application processes over the system at an early stage in application design. Once a user has defined a performance scenario, it is saved to a data model as a number of interdependent persistent objects that show the distribution of the application for a particular performance scenario from different views. Multiple alternates of each object can be stored. The user can construct different performance scenarios for analysis from the stored objects. Analysis can include performance simulation from which the user can obtain performance projections for an application process or several application processes over different distributions of the performance worload.

Abstract: A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.

Abstract: A control unit having at least one microprocessor for receiving input data signals from sensors indicative of operating parameters of the at least one system, and for generating first control signals to control operation of said at least one system in response to said input data signals. At least one input/output unit is coupled to receive the input data signals from the sensors in a parallel transmission format and to transmit output control signals to the systems in a parallel transmission format. A backup logic system provides backup control signals when transmission of the control signal is interrupted.

Abstract: A method for power net analysis of integrated circuits is provided. A circuit simulator determines current values for integrated circuit devices at specified supply voltages. A power net simulator uses the current values to calculate characteristics of the power net. The characteristics include voltage drop, current density and ground bounce. A layout representation of the power net is shown on a computer display along with the user-specified characteristics.

Abstract: Disclosed is a method and apparatus for designing re-useable interfacing logic hardware shells which provide interface functions between a hardware core and one or more busses. An interface logic hardware shell provides previously characterized, tested and implemented interface logic designs for use in future applications with little or no redesign. The hardware circuitry (cells) of which such shells are comprised includes circuitry for bus interface units, memory interface units, buffers, and bus protocol logic. The cores for which the shells provide interface functions include CPU cores, memory cores, digital video decoding cores, digital audio decoding cores, ATM cores, Ethernet cores, JPEG cores and other data processing cores.

Abstract: A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.

Abstract: A method and apparatus for emulating a digital cross-connect switching (DXC) network fully tests a telecommunication network monitoring and control system (MCS). The communication and behavior of a DXC network are emulated in the presence and absence of selected network node and trunk configurations, failures, and/or normalizations. A communication module communicates with the MCS through emulator control links using a communications protocol substantially identical to a communications protocol used in the emulated digital cross-connect network. A configuration database stores configuration data representing the current behavior of the DXC nodes. A topology database stores flexible topology data identifying trunks through adjacent DXC nodes. Changes to trunk connections can be made without knowledge of intermediate site and equipment topology details to test many network scenarios. An emulator message generator generates messages emulating communications from DXC nodes to the MCS.

Abstract: A network failure simulation tool provides simulation of a network failure suitable for automated software testing under software control. The tool intercepts packets being sent or received by a computer on a network by redirecting the packets from a network I/O architecture to substitute packet handlers. The tool also resumes normal network operation by again directing packets through actual packet handlers of the computer's network I/O architecture. Commands are provided for controlling suspension and resumption of network operation by the tool from an automated software testing program.

Abstract: A custom simulation engine is provided which operates upon a set of statically scheduled events. The simulation engine is automatically created from a functional description of the integrated circuit design. Each element of each partition within the functional description is analyzed and events related to the element are scheduled. The statically scheduled events are used to produce scheduled source code, which is then compiled to produce the simulation engine. VHDL or Verilog descriptions are similarly automatically created from the functional description. Subsequently, the VHDL or Verilog descriptions are synthesized into a netlist describing a final design of an integrated circuit. The entire process is automatic, and so the simulation engine and the netlist are functionally equivalent by construction. No simulation of the VHDL or Verilog descriptions is required as the present simulation engine correctly represents the design. Manual development of a custom simulation engine is eliminated.

Abstract: One CKD track on a direct-access storage device is divided into a plurality of fixed-length FBA blocks, only a home address HA of the CKD track and a record R0 having a CKD format are recorded in the leading FBA block, and each field (a COUNT field, KEY field and DATA field) of records R1, R2, . . . having the CKD format is recorded in the other FBA blocks. This arrangement is such that even if a format-write processing instruction for format-write from the record R1 is received from a host device, a disk control unit will not read the FBA block of HA/R0 out to a cache memory and will read out only FBA blocks from record R1 onward. As a consequence, write processing from record R1 onward can be performed in memory with ease and format-write processing can be executed at high speed.

Abstract: A computer-implemented method for executing a computer file in a CPU emulator (154) to detect a computer virus. The method includes simulating (302) the execution of a predetermined number of instructions of the computer file in the CPU emulator (154), suspending (303) the execution, constructing (304) a state record, temporarily storing (305) the state record in memory, comparing (306) the constructed state record to state records stored in a state cache (158), and indicating (308) that the file is virus free when the constructed state record matches one of the stored state records.

Abstract: When a component is placed on a circuit board, a placement position is determined by method of elastic center. Then, it is determined whether the component was placed on the circuit board. After that, connectors are routed between the component and a design candidate component which is already placed. After that, the next component is set, and the above mentioned packaging processing is repeated.

Abstract: The inventive software device simulates the cycles of a digital device on a computer system. The inventive simulator allows model bits to be computed in parallel and provides improved time-to-solution performance. The simulator uses words and bit-wise operations of the computer as vector processors. The simulator creates abstract representations having inputs and outputs for each component within the digital device. The simulator sorts the abstract representations to form groups of identical representations. Then, the simulator sequentially assigns each output of each representation in the group to one or more output words for that group. The concatenation of the output words for all groups is the output vector for the simulation. Next, the simulator maps each output bit to one or more offsets in an input vector for the simulation. Then, the simulator generates CPU instructions for each group that perform the bit calculations done by the represented component.

Abstract: A method of manufacturing a semiconductor device wherein the device is manufactured according to extracted process parameters. The process parameters are extracted as a set of optimum process parameters which satisfy an intended specification using process functions. The process functions describe a characteristic of the semiconductor device, and are determined using experimental values and/or simulated values. The process parameters may then be transmitted online to a factory.

Abstract: A method for accurately and efficiently simulating power behavior of digital VLSI MOS circuit at the gate-level. The method characterizes both the static and dynamic power consumed by a cell for different logic state conditions on all its ports. For each state-vector, power-consumption measurements are carried out for different conditions of input ramp and output load. The method looks at the power behavior of each state-vector for different values of input ramp and output loads as allowed by the technology of that cell. The exhibited power behavior is then modeled in terms of power-coefficients of the power dissipation model. These power-coefficients, which are determined by the characterizer, provide a mechanism to capture the different power consumption dependencies under varying state-vector conditions, input ramp, and output load for different types of cells. The model is unique as it has the same form for all cells, but its coefficients are customizable for each power vs. input-ramp vs.

Abstract: A technique is used to implement chains into a programmable logic device. In one embodiment, the method includes solving a bin packing problem (step 105), test-placing a chain in each logic element position (step 401), forming groups of unused logic element positions (step 405), determining whether future chains can be placed in these remaining unused logic element positions (step 410), comparing each placement against a previously stored placement, and storing the logic element position of the more efficient logic element positions have been checked (step 210). In the end, a substantially optimum placement for each chain is found.