Abstract: A device includes a folded flex substrate. A memory die is connected to a first side of the folded flex substrate. A logic die is connected to a second side of the folded flex substrate. A trace routing pattern of source voltage signals is identical to a trace routing pattern of collector voltage signals.

Abstract: A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.

Abstract: A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

Abstract: A MFS type field effect transistor includes a semiconductor layer, a PZT system ferroelectric layer formed on the semiconductor layer, a gate electrode formed on the PZT system ferroelectric layer, and an impurity layer composing a source or a drain, formed in the semiconductor layer. The PZT system ferroelectric layer includes Nb that replaces a Ti composition by 2.5 mol % or more but 40 mol % or less.

Abstract: A top-emitting OLED display that includes a substrate; an array of OLED light emissive elements formed over the substrate; an encapsulating cover located over the OLED light emissive elements; and a circular light polarizer located between the encapsulating cover and the OLED light emissive elements. The present invention has the advantage that it improves the contrast and robustness of an OLED display by protecting the circular light polarizer from environmental wear and enables the application of additional structures on the top of the encapsulating cover.

Abstract: An electronic device having a semiconductor circuit formed therein includes a semiconductor device in which the semiconductor circuit is formed; and a light emitting device, formed integrally with the semiconductor device, for emitting light indicating a reference position of the semiconductor device.

Abstract: An IGBT includes a plurality of n+ doped regions (11) selectively formed in a main surface (103) of a p+ semiconductor layer (12) opposite from an n type semiconductor layer (80) without being connected to the n type semiconductor layer (80). The n+ doped regions (11) are formed in corresponding relation to and only under channel regions (CH1a-CH1d) of structures (200a-200d), respectively. This lowers the effective concentration of the p+ semiconductor layer (12) on the n+ doped regions (11) to reduce the number of holes injected from a collector layer (9) in an off state, reducing a leakage current.

Abstract: A semiconductor device mountable on a wiring board with the bottom surface being opposed to the wiring board including a semiconductor chip; a mold resin encapsulating the semiconductor chip; a first heat spreader joined to the semiconductor chip on the bottom surface side with both ends protruding from the mold resin, the first heat spreader being capable of being joined to the wiring board at both ends; and a second heat spreader joined to the semiconductor chip on a top surface side with both ends thereof protruding from the mold resin, the second heat spreader being capable of being joined to the wiring board at both ends. One of the heat spreaders is a lead frame electrically connected to the semiconductor chip. The first and second heat spreaders are substantially entirely covered with the mold resin on the bottom surface side and the top surface side, respectively.

Abstract: A semiconductor component comprises a substrate that includes wiring on a first surface. A chip is mounted on a second surface of the substrate by a die attach, the second surface opposite the first surface. A bond channel in the center of the substrate allows for electrical connection of contact pads on the wiring with bond pads arranged in a center row on the chip by wire loops. A housing made of a mold compound surrounds a backside of the chip and parts of the substrate adjacent to the wiring. The semiconductor component further comprises a rigid prepreg layer covering, as well as the wiring of the substrate and the prepreg layer being provided with openings. Each opening is arranged in such a manner that the contact pads are accessible, and solder balls are mounted on each of the contact pads through the openings.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

Abstract: The MOS type solid-state imaging device has plural pixels each of which comprises a photo-diode and a MOS transistor on a substrate. A gate electrode is formed on the channel dope layer formed in the surface of the p-type well layer. By ion implantation of n-type impurity ions via the gate electrode as the mask, the n-type source region and the drain region are formed in the region corresponding to the MOS transistor, and the n-type impurity region is also formed in the region corresponding to the photo-diode. In the well layer, a high impurity density region as a hole pocket is self-aligned to the gate electrode.

Abstract: A substrate for mounting a semiconductor chip is formed as a multilayer substrate by alternately laminating insulation layers and wiring layers. Wires of the wiring layers are electrically connected through a via-hole for interlayer continuity. A through-hole provided through the insulation layer of the outermost surface layer is formed. A bump is inserted in the through-hole to a bump allocating position of the semiconductor chip to be mounted in the insulation layer of the outermost surface layer. A portion of the wire in the wiring layer of the outermost surface layer is projected to the internal side of through-hole at the aperture of the through-hole.

Abstract: A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in forming the emitter. This produces an economically viable high performance alternative to SiGe HBTs or SiGe retrograde base transistors.

Abstract: A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitter prior to siliciding the structure. The presence of the passivation layer in the structure prevents silicide shorts from occurring by eliminating bridging between adjacent silicide regions; therefore improved SiGe bipolar yield is obtained. A method for forming such a structure is also provided.

Abstract: A light emitting device which is capable of suppressing deterioration by diffusion of impurities such as moisture, oxygen, alkaline metal and alkaline earth metal, and concretely, a flexible light emitting device which has light emitting element formed on a plastic substrate. On the plastic substrate, disposed are two layers and more of barrier films comprising a layer represented by AlNxOy which is capable of blocking intrusion of moisture and oxygen in a light emitting layer and blocking intrusion of impurities such as an alkaline metal and an alkaline earth metal in an active layer of TFT, and further, a stress relaxation film containing resin is disposed between two layers of barrier films.

Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: Semiconductor devices in an optoelectronic integrated circuit are electrically isolated from each other by using planar lateral oxidation to oxidize a buried semiconductor layer vertically separating the semiconductor devices.