Abstract: A light-emitting diode capable of making its light emission more uniform without too high a concentration current and of improving the efficiency of outgoing light and its life. In the light-emitting diode, the n-side electrode has an n-side connecting portion and an n-side extending portion, which extends in the longitudinal direction from a predetermined part of the n-side connecting portion, and the p-side pad member has at least a p-side connecting portion to be connected to a conductive member. The light-emitting diode further includes an n-side connecting area, in which the n-side connecting portion is provided, provided in proximity to one end in the longitudinal direction, a p-side connecting area, in which the p-side connecting portion is provided, provided in proximity to another end in the longitudinal direction, and a middle area provided between them, and the n-side extending portion is positioned in the middle area, and extends so as to be opposed to the p-side current diffusing member.

Abstract: A color filter substrate includes a transmissive base; a reflective film that is formed on the base; a plurality of coloring elements having different colors that is formed on the reflective film; and a plurality of banks formed on the reflective film between the plurality of coloring elements. The bank has a transmissive portion and a non-transmissive portion. The coloring elements are formed by jetting out droplets onto deposit regions that are defined by the banks by an inkjet technique. The transmissive portion of the bank exposes the reflective film. A sufficient area is provided for each coloring element, while a sufficient area of the reflective film is exposed.

Abstract: An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure.

Abstract: A semiconductor package has a base member made of a wiring board or a lead frame, a wall member fixed onto the base member to define a cavity, and a cured-resin cap member for encapsulating a semiconductor chip in the cavity. The curable-resin cap member is fixed onto the wall member by the curing process for the curable-resin cap member.

Abstract: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (810) is sensed by sensors (820) that output electrical signals in response to the analyte. The electrical signals may be preprocessed (830) by filtering and amplification. In one embodiment, a plurality of sensors are formed on a single integrated circuit. The sensors may have diverse compositions.

Abstract: In an ESD protection device making use of a LVTSCR-like structure or an IGBT-like structure, negative polarity over-voltage protection is achieved by providing a LVTSCR-like structure or IGBT-like structure that defines a PMOS device.

Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device.

Abstract: A device and corresponding method are provided. The device includes an n-type transistor fabricated over a substrate, the n-type transistor having a gate and two current-carrying electrodes. The device also includes a non-inverted organic light emitting device fabricated over the substrate, the non-inverted organic light emitting device having an anode and a cathode. The cathode is connected to one of the current-carrying electrodes of the n-type transistor.

Abstract: An electronic component with shielding is described. The component has a semiconductor chip with a semiconductor substrate. Disposed in a region of a rear side of the semiconductor substrate is an electrically conductive buried layer. The buried layer is connected via a ground lead, disposed within the semiconductor substrate, to a contact area and an external ground potential. Furthermore, the invention relates to a method for producing an electronic component of this type.

Abstract: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon. A transparent plate having the same shape and the same size as those of the semiconductor substrate when viewed as a plan view is bonded to the surface of the semiconductor substrate. A plurality of bonding pads are formed on the surface of the semiconductor substrate and arranged around the image-pickup area. Further, a plurality of through holes are formed through the semiconductor substrate, extending from the lower surfaces of the bonding pads to the back surface of the semiconductor substrate. An insulating film is tightly attached to the inner surface of each of the through holes, while another insulating film is tightly attached to the back surface of the semiconductor substrate.

Abstract: A pixel includes five transistors, a photodetector and a storage node. A first transistor is coupled between the photodetector and the storage node. A second transistor includes a second transistor source and a second transistor drain. The second transistor source is coupled to the storage node. The second transistor drain is coupled to an output drain voltage. A third transistor includes a third transistor drain. The third transistor is coupled between the photodetector and a pixel reset voltage. The third transistor drain is coupled to the pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Abstract: A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.

Abstract: An array of light-sensitive sensors utilizes bipolar phototransistors that are formed of multiple amorphous semiconductor layers, such as silicon. In the preferred embodiment, the bipolar transistors are open base devices. In this preferred embodiment, the holes that are generated by reception of incoming photons to a particular open base phototransistor provide current injection to the base region of the phototransistor. The collector region is preferably an intrinsic amorphous silicon layer. The phototransistors may be operated in either an integrating mode in which bipolar current is integrated or a static mode in which a light-responsive voltage is monitored.

Abstract: Method of fabricating a semiconductor package and semiconductor package containing an integrated circuit chip having, on one front face, electrical connection regions, in which a first multilayer plate (2) comprising an assembly face (2a) is furnished with an adhesive layer (8) and which has through-holes (9); and a second plate (3) has a recess (13) made in one assembly face (3a) fastened to the assembly face of the first plate via the said adhesive layer; the said chip (4) being placed in the said recess in a position such that its front face is fastened to the assembly face of the first plate via the said adhesive layer and that its electrical connection regions are located facing the through-holes of this first plate, and the bottom of the recess of the said second plate bearing against the rear face of the chip opposite the front face.

Abstract: A light emitting device has a substrate, an LED mounted on the substrate. A first transparent layer seals the LED, and a second transparent layer is provided around the first transparent layer. Particles of fluorescent material are included in the second transparent layer. A reflector layer is formed on outside walls except an upper side.

Abstract: A method for manufacturing an organic thin-film transistor, comprising a substrate, a gate electrode, a gate insulation layer, an organic semiconductor layer, a source electrode and a drain electrode, is disclosed, wherein the method comprises the steps of forming the gate electrode on the substrate, forming the gate insulation layer on the substrate, forming the semiconductor layer on the substrate, applying a metal particle dispersion containing metal particles on the substrate, gate insulation layer or organic semiconductor layer to form an electrode precursor layer comprised of the metal particles, and heat-fusing the metal particles in the electrode precursor layer to form the source electrode and the drain electrode.

Abstract: A quantum semiconductor device including quantum dots formed by S-K growth process taking place in a heteroepitaxial system wherein the relationship between the energy level of light holes and the energy level of heavy holes in the valence band is changed by optimizing the in-plane strain and the vertical strain accumulated in a quantum dot.

Abstract: A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate; a plurality of storage conductors formed on the substrate, each storage conductor including a plurality of branches; a gate insulating layer formed on the gate line and the storage conductor; a semiconductor layer formed on the gate insulating layer; a data conductor formed on the semiconductor layer; a passivation layer formed on the data conductor; and a pixel electrode formed on the passivation layer, wherein at most one of the branches of each storage conductor has an isolated end.

Abstract: The present invention is an input/output (I/O) structure for an integrated circuit device which increases the input signal energy transfer characteristic and allows for increased operating frequency of the device. The I/O structure includes a conductive region in a doped region below a semiconductor bond pad. The I/O structure also includes a tapped region coupled to a supply voltage. The I/O structure may also include an output driver transistor layout with a tapped source region to decrease a parasitic series resistance between a drain region and a source voltage.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.