Abstract: A lead frame is provided. Although there is a die pad (2) located to deviate from a main plane center line of a resin molding area (10), a die pad connecting portion (6) is located to deviate from the main plane center line of the resin molding area in a direction opposite to the deviation direction of the deviated die pad (2), so that it is possible to reduce a Z-directional vertical variation of the die pad in processes. Accordingly, it is possible to prevent resin molding defects such as package bending, voids, failure of resin filling, wire disconnection, exposure of semiconductor chips, and exposure of die pads.

Abstract: The invention provides an ESD protection structure, compatible with the bipolar-CMOS-DMOS (BCD) processes, which provides an enhanced protection performance and better heat dissipation performance. The design of the ESD structures in present invention takes advantage of bipolar punch characteristics of the parasitic bipolar structure to bypass the ESD current, thus significantly reducing the trigger voltage and increasing the ESD protection level. In addition, the ESD protection circuit of the present invention can improve heat dissipation by avoid current crowding near the surface.

Abstract: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon. A transparent plate having the same shape and the same size as those of the semiconductor substrate when viewed as a plan view is bonded to the surface of the semiconductor substrate. A plurality of bonding pads are formed on the surface of the semiconductor substrate and arranged around the image-pickup area. Further, a plurality of through holes are formed through the semiconductor substrate, extending from the lower surfaces of the bonding pads to the back surface of the semiconductor substrate. An insulating film is tightly attached to the inner surface of each of the through holes, while another insulating film is tightly attached to the back surface of the semiconductor substrate.

Abstract: A SAW apparatus is provided capable of realizing a small size without adverse affect while mounting the active surfaces of the semiconductor integrated circuit and the surface acoustic wave element. The SAW apparatus comprises a semiconductor IC and a SAW element. The semiconductor IC is flip-chip mounted on a bottom of the package, a non-active surface of the SAW element is bonded to a non-active surface of the semiconductor IC by using an adhesive, and an electrode portion arranged in the active surface is wire-bonded to an electrode pattern formed on the side walls of the package by using wires.

Abstract: Within both a field effect transistor (FET) device and a method for fabricating the field effect transistor (FET) device there is provided: (1) a semiconductor substrate; (2) a gate electrode formed over the semiconductor substrate and covering a channel region within the semiconductor substrate; and (3) a pair of source/drain regions formed within the semiconductor substrate and separated by the channel region within the semiconductor substrate. Within both the field effect transistor (FET) device and the method for fabricating the field effect transistor (FET) device, at least one of: (1) an interface of the channel region covered by the gate electrode; and (2) an upper surface of the gate electrode, is corrugated.

Abstract: A semiconductor energy detector includes a semiconductor substrate comprised of a semiconductor of a first conductivity type, into which an energy ray of a predetermined wavelength range is incident from an incident surface thereof. A semiconductor energy detector includes a plurality of diffusion regions of a second conductivity type comprised of a semiconductor of a second conductivity type and a diffusion region of the first conductivity type comprised of a semiconductor of the first conductivity type higher in impurity concentration than the semiconductor substrate. The diffusion regions of a second conductivity type and the diffusion region of the first conductivity type are provided on a surface opposite to the incident surface of said semiconductor substrate. Each first conductivity type semiconductor substrate side of pn junctions, formed at the area of interface between the semiconductor substrate and each of the diffusion regions of the second conductivity type, is commonly connected.

Abstract: A memory module includes a substrate having a common substrate body, a plurality of first memory chips located over a surface of the common substrate body, a conductive pattern which electrically connects at least some of the plurality of first memory chips, and an external terminal which is electrically connected to the conductive pattern. The memory module further includes at least one second memory chip mounted over a respective one of the plurality of first memory chips and electrically connected to the conductive pattern, where each one of the plurality of first memory chips mounted below the at least one second memory chip is disabled.

Abstract: A capped chip is provided which includes a chip and a cap member, the chip having a front surface and a plurality of bond pads exposed at the front surface, the cap member having a bottom surface facing the front surface of the chip and having a top surface opposite the front surface. A plurality of through holes extend from the bottom surface of the cap member to the top surface. The capped chip assembly further includes a plurality of metallic interconnects extending from the bond pads at least partially through the through holes, the metallic interconnects including stud bumps joined to the bond pads, the stud bumps contacting and engaging at least one of (i) the top surface of the cap member surrounding the through holes and (ii) inner surfaces of the through holes.

Abstract: The present invention discloses a nonvolatile memory device which can improve the data storage capacity without increasing the surface area of the device, and a method for manufacturing the same. The nonvolatile memory device comprises: a gate of a stack type structure formed on an active region of a semiconductor substrate; a source/drain formed in the substrate at both sides of the gate of the stack type structure; an interlayer insulating film formed on the substrate where the source/drain is formed and covering the gate of the stack type structure; a contact connected to the source/drain through the interlayer insulating film; a plurality of conductive patterns formed in the interlayer insulating film of the region not adjacent to the contact; and an electrode pad formed on the conductive patterns.

Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

Abstract: Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion of the thin semiconductor and insulating layers. Source/drain stressors are then formed contacting the source/drain extensions on opposing sides of the pedestal and substantially spanning a height no less than the pedestal.

Abstract: An aspect of the present invention provides a heat sink has a side with a pattern that extends at least partially through a thickness of the heat sink. The heat sink also has a thickness no greater than 9 mm. In another embodiment, a heat sink has a side with a pattern that extends at least partially through a thickness of the heat sink. The heat sink also has a ratio of area:thickness, as seen from a plan view, of at least 500:1 when the area and thickness are expressed in units of mm2 and mm, respectively.

Abstract: In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.

Abstract: A multiple supply gate array structure facilitated by the provision of a shared n-well and an isolated n-well is described. The gate array structure allows implementation of a single voltage circuit or a multiple voltage circuit. In addition, the gate array structure allows metal reprogram to provide standard logic functions, or special logic functions such as a buffer function for a signal crossing a voltage island boundary. Other special logic functions may include, for example, a level-shifter function or a fence-hold function.

Abstract: A power semiconductor device to which a large current can be applied and which can be fabricated compactly in a shorter time, including an electrode structure for taking out electrodes from a power semiconductor element mounted on one of a plurality of circuit patterns formed on an insulating substrate inside of a case up to an external-connection terminal exposed outside of the case, and an external-connection terminal insert-formed on the body of the case, exposed to the outside of the case at one end of the terminal and having a junction portion at its other end joined to a circuit pattern different from the circuit pattern on which the power semiconductor element is mounted. The junction portion is directly connected with the power semiconductor element through a wire member bonded to the face opposite to the junction face of the terminal.

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract: A semiconductor junction varactor is designed with gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract: An InGaN-based light-emitting diode that emits light in blue, for example, is mounted on a support substrate as a semiconductor light-emitting element, and a transparent film is fixed to the support substrate so as to cover the semiconductor light-emitting element. An electrode pattern is formed on an upper surface of the transparent film, and the electrode pattern is electrically connected to terminal electrodes of the semiconductor light-emitting element through, for example, through-holes. The transparent film can contain a phosphor excited by light emitted from the semiconductor light-emitting element. It is not necessary to perform wire bonding for connecting the semiconductor light-emitting element to the electrode pattern and sealing with a sealant.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: An electrostatic discharge protection device formed on a substrate. The electrostatic discharge protection device includes a first isolation region formed over the substrate, an active region formed over the substrate and enclosed by the first isolation region, a second isolation region formed on the substrate and substantially surrounded by the active region, a first gate element formed in the active region, the first gate element having a first end extending over the first isolation region and a second end extending over the second isolation region, a drain region formed in the active region at a first side of the first gate element, a source region formed in the active region at a second side of the first gate element, a drain contact for electrically coupling the drain region to a first node, and a source contact for electrically coupling the source region to a second node.