Abstract: Disclosed are an upper substrate structure for a plasma display panel including a dielectric layer reinforcing color properties and a fabricating method thereof. The upper substrate structure comprises a sustain electrode formed on an upper glass substrate, a bus electrode formed on the sustain electrode, and an upper substrate dielectric layer formed over a lower part of the surface created by two electrodes and the glass substrate. There is also included a colorant having color properties of red, blue, and green colors, and a protection layer formed on the dielectric layer. The dielectric layer may include one or more colorants so that important properties of PDP such as selective brightness of desired color, color temperature, and color purity improvement can be controlled.

Abstract: The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same conductivity. A highly doped first well zone of the first conductivity and a highly doped second well zone of a second conductivity are arranged between the drift zone and the semiconductor substrate.

Abstract: A new use for a structure including a plurality of nozzles extending through the structure, and the nozzles being spaced from each other in correspondence with the pattern to be deposited onto an OLED display substrate so that vaporized organic material is transported through the nozzles in a desired pattern for deposition onto the OLED display substrate.

Abstract: In order to provide an electro-optical device and a semiconductor device each having a connecting portion with a structure capable of reducing or preventing reliability from deteriorating and allowing circuits to be highly integrated, a connecting portion a first conductive layer formed on a first insulating film, a second insulating film formed to cover the first conductive layer, a second conductive layer formed on the second insulating film and a contact hole penetrating the second insulating film and the first insulating film. Wiring lines are electrically connected to each other because the first conductive layer contacts the second conductive layer on the side surface of the contact hole. Further, an etching stop layer that has a tolerance against etching of the first insulating film is disposed on a region corresponding to at least the bottom surface of the contact hole.

Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.

Abstract: A light emitting device includes a region of first conductivity type, a region of second conductivity type, an active region, and an electrode. The active region is disposed between the region of first conductivity type and the region of second conductivity type and the region of second conductivity type is disposed between the active region and the electrode. The active region has a total thickness less than or equal to about 0.25?n and has a portion located between about 0.6?n and 0.75?n from the electrode, where ?n is the wavelength of light emitted by the active region in the region of second conductivity type. In some embodiments, the active region includes a plurality of clusters, with a portion of a first cluster located between about 0.6?n and 0.75?n from the electrode and a portion of a second cluster located between about 1.2?n and 1.35?n from the electrode.

Abstract: The present invention discloses a structure of light-emitting diode (LED) array module, comprising a substrate, a carrier substrate, a chip, a driving circuit chip, and a plurality of metal lines. The carrier substrate is on top of the substrate, and the top surface of the carrier substrate is divided into a first area and a second area. The chip is attached to the first area of the carrier substrate, and further comprising a light-emitting component array and a pad array. The driving circuit chip is attached to the second area of the carrier substrate, and further comprising a pad array and a pad. The metal lines are for electrically connecting the substrate to the driving circuit chip, and the chip to the driving circuit chip, respectively. The present invention can reduce the manufacturing cost, and improve the yield rate.

Abstract: A recessed portion of an adhesive is formed between a wiring board and a heat spreader. Voids occur in the neighborhood of the top of each metal thin wire upon curing an encapsulating resin, thus causing a reduction in moisture resistance. Therefore, the present invention provides a semiconductor device wherein a semiconductor chip and a wiring board are fixed to a heat spreader by an adhesive layer formed over a principal surface of the heat spreader, by using a method such as thermocompression bonding to thereby eliminate a recessed portion, and the parts are sealed with an encapsulating resin inclusive of the semiconductor chip and the metal thin wires.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: An abrasive for a semiconductor device comprises cerium oxide particles and coating materials. The cerium oxide particles are made principally of cerium oxide (CeO2). The coating materials cover the surface of the cerium oxide particles.

Abstract: A temperature-protected semiconductor switch having a semiconductor switch element composed of a number of cells connected in parallel and an integrated reverse diode, and further having a temperature sensor wherein the semiconductor switch element and the temperature sensor are integrated together in a semiconductor body of a first conductivity type. Upon occurrence of an excess temperature, the temperature sensor generates a first signal. A charge carrier detector is also provided which generates a second signal given the occurrence of free charged carriers caused by the integrated reverse diode in the semiconductor body. The first and second signals are supplied to an evaluation means that, for examples, undertakes the shut-off of the semiconductor switch only in the case of a true excess temperature.

Abstract: A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.

Abstract: Semiconductor devices include a wide bandgap semiconductor layer having an array of discontinuous wide bandgap semiconductor regions therein that contribute to a reduction in ionization energies of dopants in the wide bandgap semiconductor layer relative to an otherwise equivalent wide bandgap semiconductor layer that is devoid of the array of discontinuous wide bandgap semiconductor regions. The discontinuous wide bandgap semiconductor regions and the wide bandgap semiconductor layer have the same net conductivity type, but the discontinuous wide bandgap semiconductor regions are typically more highly doped to thereby provide excess charge carriers to the wide bandgap semiconductor layer.

Abstract: There is provided a susceptor with a built-in electrode and a manufacturing method therefor, in which there is no danger of corrosive gas or plasma or the like penetrating to the inside of the substrate, which has excellent corrosion resistance and plasma resistance, in which nonconductivity under high temperatures is improved, and in which leakage current does not occur.

Abstract: Device 60 in FIG. 3 has junctions 86 each with a lateral portion 90 and a second portion 92 extending upward toward the surface 12 from the lateral portion 90. The lateral portions 90, as illustrated in FIG. 3, are more or less formed along a plane parallel with the surface 12. The upwardly extending portions 92 include characteristic curved edges of the diffusion fronts which are associated with the planar process. With the regions 80 and 82 each having relatively high net dopant concentrations of different conductivity types, each lateral junction portion 90 includes a relatively large sub region 96 which extends more deeply into the layer 10. When compared to other portions of the junctions 86, the subregions 96 are characterized by a relatively low breakdown voltage so that ESD current is initially directed vertically rather than laterally.

Abstract: An organic light emitting diode (OLED) light source comprises a plurality of groups of OLEDs, the OLEDs in each group being electrically connected in parallel, and the groups being electrically connected in series.

Abstract: Micromirror devices, especially for use in digital projection are disclosed. Other applications are contemplated as well. The devices employ a superstructure that includes a mirror supported over a hinge set above a substructure. Various improvements to the superstructure over known micromirror devices are provided. The features described are applicable to improve manufacturability, enable further miniaturization of the elements and/or to increase relative light return. Devices can be produced utilizing the various optional features described herein, possibly offering cost savings, lower power consumption, and higher resolution.

Abstract: A power semiconductor device includes a base layer of first conductivity. A base layer of second conductivity is selectively formed on one surface of the base layer of first conductivity. An emitter layer or source layer of first conductivity is selectively formed on the surface of the base layer of second conductivity. A collector layer or drain layer is selectively formed on the other surface of the base layer of first conductivity or selectively formed on the one surface thereof. A gate electrode is formed on first and second gate insulating films which are formed on part of the base layer of second conductivity which lies between the emitter layer or source layer of first conductivity and the base layer of first conductivity. The capacitance of a capacitor formed of the second gate insulating film is different from that of a capacitor formed of the first gate insulating film.

Abstract: A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region.

Abstract: The controllable semiconductor switching element blocks in both directions. The semiconductor switching element is formed with a first conduction region and a second conduction region of a first type of conductivity, a blocking region of a second type of conductivity which is disposed between the first and second conducting regions, and a control electrode which is arranged opposite the blocking region and insulated from it. A recombination region is configured in the blocking region and is comprised of a material that promotes a recombination of charge carriers of the first and second type of conductivity.