Abstract: Techniques providing data path strategies for improving storage performance at DR sites. The techniques include receiving, in an asynchronous replication process, a large replication data transfer including data changes of a production volume since the last synchronization to a replica volume, partitioning the replication data into multiple small write requests, tagging each small write request as a write request to the replica volume, and performing early evicting, from cache memory, all cache pages used to cache host data specified in the small write requests; deep compression of contiguous host data specified in the small write requests; stream separation on the small write requests, each small write request being tagged as corresponding to a specific production site; and/or flushing host data having the same retention period to a specific region of physical storage space for the replica volume, each small write request being tagged with hint information indicating the retention period.

Abstract: Provided is a method for managing a data migration operation, including creating, by a storage device, a read submission queue entry indicating a location of data at a source storage of the storage device to be copied from the source storage to a target storage, the read submission queue entry including a field including metadata including information for reading the data from the source storage.

Abstract: A specification of content to be stored in a cloud storage is received at a client-side component. A first portion of the content is divided into a plurality of data chunks. One or more data chunks of the plurality of data chunks that are to be sent via a network to be stored in the cloud storage are identified. It is determined whether a batch size of the one or more identified data chunks does not meets a threshold size. One or more data chunks of a second portion of the content that are to be stored in the cloud storage are identified. It is determined that a size of a second batch of data chunks that includes the one or more identified data chunks of the first portion of the content and the one or more identified data chunks of the second portion of the content does not meet the threshold size. It is determined that a batch period is greater than or equal to a batch threshold period. The second batch of data chunks is written to a storage of a cloud server included in a data plane.

Abstract: Techniques are provided for hosting a key value store. A persistent storage backend is used to centrally host a key value store as disaggregated storage shared with a plurality of clients over a network fabric. A network storage appliance is connected to the plurality of clients over the network fabric, and is configured with a key value store interface. The key value store interface is configured to receive a key value command from a client. The key value store interface parses the key value command to identify a translation layer binding for a key value store targeted by the key value command. The key value store interface translates the key value command into a key value operation using the translation layer binding, and executes the key value operation upon the key value store.

Abstract: A system includes a plurality of processing elements and a plurality of memory controllers. The system includes a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers. The NoC includes a sparse network coupled to the plurality of processing elements and a non-blocking network coupled to the sparse network and the plurality of memory controllers. The plurality of processing elements execute a plurality of applications. Each application has a same deterministic memory access performance in accessing associated ones of the plurality of memory controllers via the sparse network and the non-blocking network of the NoC.

Abstract: A software-RAID-protected boot data vSAN system includes a chassis housing a software RAID subsystem coupled to storage devices and to controller devices. The software RAID subsystem designates a RAID controller device and a vSAN controller device from the controller devices, and configures a first subset of the storage devices for boot storage and a second subset of the storage devices for vSAN storage. The software RAID subsystem then provides a RAID path from the RAID controller device to the boot storage provided by the first subset of the storage devices, and provides a vSAN path from the vSAN controller device to the vSAN storage provided by the second subset of the storage devices. The software RAID subsystem then routes boot storage commands along the RAID path, and routes vSAN storage commands along the vSAN path.

Abstract: An electronic device is provided. The electronic device includes a storage, a volatile memory, and a processor, wherein the processor is configured to identify temperature information based on a temperature of the volatile memory and a temperature of the processor, to identify a first temperature section corresponding to the temperature information among a plurality of predetermined temperature sections, to perform calibration of the volatile memory to acquire an operation parameter corresponding to the first temperature section, and to adjust a timing between signals for controlling an operation of the volatile memory based on the operation parameter.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Abstract: A storage device may generate mapping information between a plurality of memory regions and one or more namespaces. The storage device may record information on empty memory regions among the plurality of memory regions in an empty table, and may determine empty memory regions to be mapped to a target namespace among the empty memory regions recorded in the empty table.

Abstract: Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

Abstract: An illustrative method includes receiving, by a container storage interface (CSI) filter driver executing on a node of a cluster managed by a container orchestrator, a request to deploy a containerized application; selecting, by the CSI filter driver based on one or more attributes of the containerized application, a storage system from a plurality of storage systems attached to a plurality of clusters managed by the container orchestrator; and transmitting, by the CSI filter driver, a command to a CSI driver executing on a node of a cluster to which the storage system is attached, the cluster included in the plurality of clusters, the command configured to direct the CSI driver to provision a volume on the storage system for use with the containerized application.

Abstract: In at least one embodiment, processing can include receiving, at a first node, a read request directed to a logical address LA owned by a second node. The first node can locally cache content and an address hint corresponding to LA. The first node can issue a request to the second node. The request can include a flag to suppress the second node from returning content stored at the target logical address. The first node can receive a response including an address used to read current content of LA1 from back-end non-volatile storage. The first node can determine whether the address matches the address hint cached on the first node. If the first node determines the address and address hint match, the cached content of LA stored on the first node is valid and can be returned in response to the read as current content stored at LA.

Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.

Abstract: A device controller of a storage device including a non-volatile memory peeks a command from a submission queue, and determines whether the peeked command is executable based on a status of device resources. In response to determining that the command is executable, the device controller fetches the command, allocates the device resources to the fetched command, and executes the command.

Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.

Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is coupled to the flash memory device through the specific communication interface, and used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array and to make the flash memory device determine whether the multiple page units are empty pages.

Abstract: Disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. Usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. For example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. This improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.

Abstract: There is provided mechanisms for initiating writing data of a pending memory write on a host computer. A method comprises monitoring pending memory writes for a non-volatile memory write indicator (NVMWI). The NVMWI is either set or not set. The method comprises initiating writing of the data of the pending memory write. Writing of the data is initiated to both a non-volatile memory (NVM) and a volatile memory (VM) when the NVMWI for the pending memory write is set. Writing of the data otherwise is initiated only to the VM.

Abstract: The present disclosure provides a data processing circuit and method, and a semiconductor memory, relating to the field of storage technologies. The circuit includes: a data selection module configured to receive and output write data if a received write control command is in a first level state, and receive and output read data if a received read control command is in the first level state; a check module configured to receive the write data or the read data, check the write data or the read data, and obtain write check data or read check data, and output the write check data or the read check data; and a data output module configured to receive the write check data or the read check data, output the write check data if the write control command is in the first level state.