Patents Examined by Daniel C Chappell
  • Patent number: 11340784
    Abstract: Described is a system for detecting corruption in a deduplicated object storage system accessible by one or more microservices while minimizing costly read operations on objects. A controller module and one or more worker nodes execute verification paths in concert with each other to identify object corruptions. The controller module estimates a number of worker nodes required for execution of different types of verification paths.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 24, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Tipper Truong, Joseph Brandt, Philip Shilane
  • Patent number: 11341039
    Abstract: A data arrangement method of a flash memory, a flash memory storage device, and a flash memory control circuit unit are provided. The method may be applied to a flash memory, an embedded memory device, or a solid-state disk having a three-dimensional (3D) structure. The method includes: executing a background garbage collection operation in a background mode; receiving at least one write command from a host when the background garbage collection operation is not completed to suspend the background garbage collection operation and exit the background mode; executing the at least one write command; and entering the background mode and continuing the execution of the background garbage collection operation after the at least one write command is completed. Therefore, execution efficiency of the write command in a foreground mode may be optimized.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: May 24, 2022
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Zhi Wang, Yan Zheng, Xiaoyang Zhang, Kai-Di Zhu
  • Patent number: 11334267
    Abstract: A disclosed method may include (1) detecting one or more requests for a memory chunk of a specific size on a computing device, (2) determining that the computing device has yet to implement a memory pool dedicated to fixed memory chunks of the specific size, (3) computing an amount of memory that is potentially wasted in part by satisfying the one or more requests from an existing memory pool dedicated to fixed memory chunks of a different size, (4) determining that the amount of memory that is potentially wasted exceeds a waste threshold, and then in response to determining that the amount of memory that is potentially wasted exceeds the waste threshold, (5) creating an additional memory pool dedicated to fixed memory chunks of the specific size on the computing device. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 17, 2022
    Assignee: Juniper Networks, Inc
    Inventors: Amit Kumar Rao, Erin C. MacNeil, Finlay Michael Graham Pelley
  • Patent number: 11334493
    Abstract: A memory system includes: a memory device including a plurality of memory blocks; and a controller for dynamically changing a size of a write buffer based on whether a current workload is a sequential workload or a mixed workload, wherein the controller includes: a workload detecting unit suitable for changing current workload from the sequential workload to the mixed workload based on a read count, or from the mixed workload to the sequential workload based on a write count; and a write buffer managing unit suitable for reducing the size of the write buffer when the current workload is changed to the mixed workload.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 17, 2022
    Assignee: SKhynix Inc.
    Inventors: Jooyoung Lee, Hoeseung Jung
  • Patent number: 11334283
    Abstract: A method for providing application data of at least one application executable on a control unit of a vehicle. The control unit includes components for running an operating system including a virtual memory management. In the method, an application address space of a first virtual memory is initially read out, the application address space being assigned to a process of the application and representing an area of a physical memory of the control unit occupied by the application data. The application address space is mapped in a further step into a virtual address space, which is assigned to a process of a communication application for exchanging data via a communication interface to a control unit-external evaluation unit. The application data are therefore retrievable via the communication interface.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 17, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Florian Kraemer, Maksym Shchetynin, Michael Deckert, Patrick Nagel
  • Patent number: 11327653
    Abstract: A storage system for continuing I/O without affecting drive box addition to a host computer includes: a plurality of drive boxes for connecting to a computer device that transmits commands for data reads or writes; and a storage controller connected to the drive boxes. A first drive box provides a first storage region to the computer device. The storage controller manages correspondence between the first storage region and a physical storage region of the drives constituting the first storage region. The first drive box receives a command for the first storage region from the computer device and transfers the command to the storage controller. The storage controller generates a data transfer command including a data storage destination based on the address management table, and transfers the command to the first drive box. The first drive box then transfers the data transfer command to the second drive box.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 10, 2022
    Assignee: HITACHI, LTD.
    Inventors: Nobuhiro Yokoi, Hirotoshi Akaike, Ryosuke Tatsumi, Koji Hosogi, Akira Yamamoto
  • Patent number: 11314648
    Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Michael Filippo, Jamshed Jalal, Kias Magnus Bruce, Alex James Waugh, Geoffray Lacourba, Paul Gilbert Meyer, Bruce James Mathewson, Phanindra Kumar Mannava
  • Patent number: 11307797
    Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 11307991
    Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 19, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Jiyun-Wei Lin
  • Patent number: 11307773
    Abstract: According to an embodiment, power demands of a computing device or component thereof may be stabilized by performing redundant operations during periods of otherwise low power demand. In so doing, the current load of the device/component remains relatively stable, potentially greatly reducing voltage droops and overshoots. This can reduce the peak voltage and peak power rating of the device/component. In certain embodiments, such as in network switches and routers, the redundant operations may include queries against a content addressable memory (CAM), such as a ternary content addressable memory (TCAM). Moreover, in an embodiment the queries may be designed to always, or at least be highly likely to, miss the entries in the CAM, thereby ensuring maximum power usage. In another embodiment, the redundant operations include read operations on a random access memory (RAM). In other embodiments, redundant operations may be performed with respect to other power-intensive subsystems.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 19, 2022
    Assignee: Innovium, Inc.
    Inventors: Keith Michael Ring, Mohammad Kamel Issa
  • Patent number: 11301391
    Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
  • Patent number: 11301151
    Abstract: A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: April 12, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Su-Chueh Lo
  • Patent number: 11301166
    Abstract: The present invention relates to a flash storage device and an operation control method therefor, and when the flash storage device or a mobile terminal on which the flash storage device is mounted is connected to an external power supply, the flash storage device detects and classifies a power supply type, and according to detection and classification information thereof, the reliability and performance of the data of the device can be improved by performing an internal operation thereof.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: April 12, 2022
    Assignee: JM SEMICONDUCTOR, LTD.
    Inventor: Wan-Ho Cho
  • Patent number: 11301139
    Abstract: Systems and methods that result in a stable storage system are provided. In the storage system, the latency spikes may be reduced when multiple volumes are aggregated into transfer sets according to system characteristics. The storage system transfers ownership of volumes in each transfer set as a single transaction. In the storage system, connectivity between the host and the storage controller is re-established based on the connectivity in a physical transport layer and a single path. In the storage system, pre-mature failback is also avoided when ownership of volumes is transferred back to a preferred storage controller when the same number of paths existed between the host and the preferred storage controller before and after a failover operation. Further, the storage system generates connectivity reports that display connectivity paths between hosts, storage controllers, and volumes.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 12, 2022
    Assignee: NETAPP, INC.
    Inventors: Mahmoud K. Jibbe, Dean Lang, Joey Parnell, Ryan Rodine, Joshua Briner
  • Patent number: 11288182
    Abstract: The invention introduces a method for multi-namespace data access, performed by a controller, at least including: obtaining a host write command from a host, which includes user data and metadata associated with one Logical Block Address (LBA) or more; and programming the user data and the metadata into a user-data part and a metadata part of a segment of a Logical Unit Number (LUN), respectively, wherein a length of the metadata part is the maximum metadata length of a plurality of LBA formats that the controller supports.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: March 29, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Che-Wei Hsu
  • Patent number: 11288007
    Abstract: Virtual physical erase of a memory of a data storage device. One example data storage device may include a flash memory. The data storage device further may include an electronic processor that may be configured to store a first portion of data in the flash memory, and receive a physical erase request from an access device. The electronic processor may be further configured to identify a first block of the flash memory and a memory fragment of the first block where the first portion of data is stored in the flash memory. The electronic processor may be further configured to, in response to receiving the physical erase request, program one or more cells corresponding to the memory fragment to an increased voltage state so as to obfuscate the first portion of data that is stored in the flash memory.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11275531
    Abstract: A management apparatus, includes a memory; and a processor coupled to the memory and configured to: manage a library device including one or more drive devices, an accommodation shelf in which accommodation cells that accommodate a plurality of tape media are arranged, and a robot that performs conveyance operation to convey the tape media between the accommodation cells and the drive devices, receive an instruction to write a plurality of pieces of writing data, set, as an erasure coding set, two or more pieces of writing data having a data size less than a threshold among the plurality of pieces of writing data, and allocate the two or more pieces of writing data to one of the plurality of tape media.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Shun Gokita
  • Patent number: 11243898
    Abstract: A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 8, 2022
    Assignee: Arm Limited
    Inventors: Andreas Hansson, Aniruddha Nagendran Udipi, Neha Agarwal
  • Patent number: 11231873
    Abstract: An apparatus is described. The apparatus includes velocity assignment logic to assign a velocity to data that is to be written to a non volatile storage medium. The velocity assignment logic is to accept input information pertaining to an identity of an application that is writing the data, the data type of the data and the state of the application in order to determine the velocity.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventor: Sanjeev N. Trika
  • Patent number: 11232040
    Abstract: Systems, devices, media, and methods are presented for selectively partitioning and precaching data elements. The systems and methods identify a device context for a client device and identify a cell based on the device context. The cell is associated with one or more partition characteristics and a plurality of data elements stored in a precache of data elements. The systems and methods select a set of data elements corresponding to the cell and at least a portion of the one or more partition characteristics. The systems and methods then retrieve the selected set of data elements from the precache of data elements and cause presentation of at least one data element of the selected set of data elements at a display device coupled to the client device.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: January 25, 2022
    Assignee: Snap Inc.
    Inventors: Samir Ahmed, Amit Gaur, Yue Hu, Manish Maheshwari, Yang Wen