Abstract: A computer-implemented method for altering a position on a tape at which the tape transitions to a DATA_FULL state is disclosed. The computer-implemented method further includes determining, after a file is written to a Data Partition of the tape, a size of an Index representing metadata associated with the file. The computer-implemented method further includes altering, based on the size of the Index representing metadata associated with the file, a position in the Data Partition of the tape at which the tape transitions to the DATA_FULL state.

Abstract: Examples described herein relate to management of containers in a storage system. Examples may receive a container specification corresponding to a container image. Examples may obtain the container image from a container repository and select storage volumes based on the container specification. Examples may execute one or more containers from the container image on a controller of the storage system within resource limits. Examples may dynamically select the controllers based on resource availability at the plurality of controllers. Examples may allow scheduling the execution of the containers at a specific controller at a predetermined time. The execution may include performing one or more batch operations on the storage volumes. Examples may further enable monitoring a status of the container and providing alerts in response to a detection of a failure event associated with the container.

Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.

Abstract: In creating an extent array in a storage system, in response to receiving a request to generate an extent array using idle extents in storage devices, a width of an extent stripe is determined, and a size of the extent array is designated by the storage system. A first extent group and a second extent group are respectively selected from the storage devices based on the width to form a first extent stripe and a second extent stripe, and a first extent at a given position in the first extent group and a second extent at a given position in the second extent group are respectively located in different storage devices. Based on the first extent stripe and the second extent stripe, an address mapping representing the extent array is generated. The address mapping includes association between extent identifiers of extents and extent indexes of the extents.

Abstract: Storage devices can be configured to utilize one or more memory buffers located within a host-computing device. These host buffers may allow for faster access to some data, including control pages. However, host buffers are susceptible to fragmentation issues similarly to standard user memory arrays. As the data stored within the host buffers becomes more fragmented, performance can suffer. This performance loss in storage devices becomes more pronounced as the desired performance levels of these storage devices increase. Therefore, various methods and systems described herein manage fragmentation within host buffers by conducting one or more operations. These operations may include locating a continuous portion of allocated or unallocated memory within the host buffer and either swap or copy high-usage or high-priority data to those continuous portions. When continuous portions of host buffer memory are not available, relevant portions of data may be cashed within the storage device to increase performance.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and accordingly record a plurality of logical addresses in a first mapping table. In response to a determination of recommending for activating one or more sub-regions of the memory device or delivering one or more Host Performance Booster (HPB) entries is required, the memory controller is further configured to update a second mapping table based on the first mapping table before delivering the HPB entries to the host device. The memory controller is further configured to generate the HPB entries according to the second mapping table after the second mapping table has been updated based on the first mapping table and deliver a packet comprising the HPB entries to the host device.

Abstract: A technique replicates an index of an operations log (oplog) from a primary node to a secondary node of a cluster in the event of failure. The oplog functions as a staging area to coalesce random write operations directed to a virtual disk (vdisk) stored on a backend storage tier. The oplog temporarily caches write data as well as metadata describing the write data. The metadata includes descriptors to the write data corresponding to offset ranges of the vdisk and are used to identify ranges of write data for the vdisk that are cached in the oplog. To facilitate fast lookup operations of whether write data is cached in the oplog, an oplog index provides a state of the latest data for offset ranges of the vdisk that enables fast failover of metadata used to construct the oplog index in memory without downtime or significant metadata replay.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A method for storing data, the method comprising receiving, by an offload component in a client application node, a request originating from an application executing in an application container on the client application node, wherein the request is associated with data and wherein the offload component is located in a hardware layer of the client application node, and processing, by the offload component, the request by a file system (FS) client and a memory hypervisor module executing in a modified client FS container on the offload component, wherein processing the request results in at least a portion of the data in a location in a storage pool.

Abstract: A communication device provides data to a data acquiring node based on a consensus of a plurality of participating nodes. The communication device includes a processor. The processor divides the data into N data components. N is an integer equal to or larger than two. When the N data components are stored in different storage areas, the processor encrypts addresses of storage areas in which the data components are respectively stored with respective public keys of N participating nodes among the plurality of participating nodes. The processor transmits access right information that indicates the data acquiring node has a right to access the data and the encrypted N addresses to the plurality of participating nodes.

Abstract: A data processing system is provided comprising a cache system configured to transfer data between a processor and memory system. The cache system comprises a cache. When a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the block of data is stored into a group of one or more cache lines of the cache and the associated compression metadata for the compressed block of data is provided as separate side band data.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved physical address obtainment speed may include a nonvolatile memory device configured to store map data including a plurality of map segments including mapping information and, a volatile memory device including a first map cache area temporarily storing the map data configured by map entries each corresponding to one logical address, and a second map cache area temporarily storing the map data configured by map indexes each corresponding to a plurality of logical addresses.

Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.

Abstract: Embodiments of the present disclosure relate to cache memory management. One or more global caches are dynamically partitioned and sized into one or more cache partitions based on anticipated input/output (IO) workloads.

Abstract: A system and method are disclosed for a cache IP that includes registers that are programmed through a service port. Service registers are selected from the registers to define an address range so that all cache lines within the address range can be flushed automatically using a control signal sent to a control register.

Abstract: A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

Abstract: Techniques for reducing unsafe memory access, particularly when interacting with native libraries, are disclosed. The system may receive a memory address. The system may determine that the received memory address is not associated with an existing memory segment. The system selects a particular memory segment, of a plurality of memory segments. The memory segment may have a length of zero and a size corresponding to a size of a native heap. The system may return a reference to the particular memory segment.

Abstract: Devices and techniques for host adaptive memory device optimization are provided. A memory device can maintain a host model of interactions with a host. A set of commands from the host can be evaluated to create a profile of the set of commands. The profile can be compared to the host model to determine an inconsistency between the profile and the host model. An operation of the memory device can then be modified based on the inconsistency.

Abstract: An electronic device according to various embodiments of the present invention comprises a host device and a block device electrically connected to the host device, wherein the block device comprises a first memory and a controller electrically connected to the first memory, and the controller receives a write request for first data form the host device, determines whether the first data is pattern data configured in a form in which an assigned number of bit values are repeated, and, in response to the first data being determined to be the pattern data, controls the first memory to store the assigned number of bit values of the first data in a logical to physical mapping table after mapping the assigned number of bit values to a logical address indicated by the write request.

Abstract: Systems and methods for generating and using a placement map for a distributed storage system are disclosed. In some embodiments, a method for a client node to perform a read/write operation in a distributed storage system comprises obtaining a number of server nodes comprised in the distributed storage system and an object name of an object for which a read/write operation is to be performed and creating at least a portion of a three-dimensional (3D) placement map for the object. The 3D placement map defines candidate locations for replicas of the object on the server nodes. The method further comprises applying policies to the at least a portion of the 3D placement map to provide at least a portion of a modified 3D placement map and performing the read/write operation for the object in accordance with the at least a portion of the modified 3D placement map.