Abstract: An apparatus includes at least one processing device configured to obtain information characterizing which of a plurality of storage nodes of a distributed storage system stores respective ones of a plurality of different logical blocks of a logical storage volume of the distributed storage system. The at least one processing device is further configured, for each of a plurality of input-output operations directed to a particular one of the logical blocks of the logical storage volume, to identify, based at least in part on the obtained information, which of the plurality of storage nodes of the distributed storage system stores the particular logical block, to select a path to the identified storage node, and to send the input-output operation to the identified storage node over the selected path.

Abstract: Techniques involve obtaining, at a first network interface card coupled with a first device, information related to a plurality of data blocks to be written to a second device, the information including sizes of the plurality of data blocks and a plurality of destination addresses in a memory of the second device where the plurality of data blocks will be written. The techniques further involve generating a write request for the plurality of data blocks based on the information, the write request indicating at least the plurality of destination addresses and the sizes of the plurality of data blocks. The techniques further involve sending the write request to a second network interface card coupled with the second device, so that the plurality of data blocks are written to the plurality of destination addresses. Such techniques reduce the number of communications thus improving system performance and reducing hardware resource consumption.

Abstract: Performance degradation of an application that is caused by another computing process that shares infrastructure with the application is detected. The application and the other computing device may execute via different virtual machines hosted on the same computing device. To detect the performance degradation that is attributable to the other computing process, certain storage segments of a data storage (e.g., a cache) shared by the virtual machines is written with data. A pattern of read operations are then performed on the segments to determine whether an increase in read access time has occurred. Such a performance degradation is attributable to another computing process. After detecting the degradation, a metric that quantifies the detected degradation attributable to the other computing process is provided to an ML model, which determines the actual performance of the application absent the degradation attributable to the other computing process.

Abstract: A hardware accelerator may be used for assisting a separate processor in performing sparse embedding vector lookup operations, each non-zero index of a sparse embedding vector referencing a respective dense embedding vector. The hardware accelerator comprises: a plurality of Dynamic Random Access Memory (DRAM) modules, each DRAM module comprising a distinct packaged device or chiplet; one or more memory controllers, each memory controller being configured to address a subset of the plurality of DRAM modules, each memory controller and associated subset of the DRAM modules defining a memory channel; and processing logic, arranged to control the one or more memory controllers. More than one dense embedding vector may be read from multiple memory channels in parallel and/or multiple copies of a dense embedding vector are stored in a memory channel.

Abstract: A computer implemented method manages virtual disks. A number of processor units detects attachment of a storage to a host operating system. The number of processor units mounts the storage to a set of mount points. The number of processor units creates a set of virtual disks and assigning, by the number of processor units, the set of virtual disks to a guest in operation in which instructions for the operation are performed without interruption. According to other illustrative embodiments, a computer system and a computer program product for managing virtual disks are provided.

Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules. The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.

Abstract: Disclosed is a microcircuit card includes a module for identification within a mobile telephone network storing a first piece of data, and a memory module storing a second piece of data. wherein the first piece of data and the second piece of data comply with a predetermined rule. Also disclosed is a method for verifying this microcircuit card when the card is housed in an electronic device includes a step of verifying that the first piece of data and the second piece of data comply with a predetermined rule, as well as methods for personalizing the microcircuit card, the microcircuit card, and the electronic device are also described.

Abstract: File number segments to be used within simulations can be defined. Tape division regions to be used within simulations can be defined. Times to locate each file number segment for each tape division region according to a first locate method can be simulated. Times to locate each file number segment for each tape division region according to a second locate method can be simulated. The simulated times for each locate method can be applied to a set of defined total file numbers to determine the time to locate each defined total file number for each locate method, file number segment, and tape division region combination.

Abstract: Embodiments of the present invention disclose a data processing solution. In this solution, a hard disk receives a call instruction sent by a server, where the call instruction includes a function identifier of a to-be-called function and an operation address; and the hard disk calls the function in the hard disk based on the function identifier, and performs, based on the function, an operation on data corresponding to the operation address.

Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.

Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract: A method includes determining one or more quality attributes for memory cells of a memory device, receiving a memory access request involving data written to at least a portion of the memory cells, and determining whether the memory access request corresponds to a random read operation or a sequential read operation. The method further includes responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation and performing the random read operation using the selected read mode.

Abstract: A memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and operate any one of different control schemes for each of the first memory blocks based on a number of first not-open (N/O) strings included in each of the first memory blocks, respectively.

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

Abstract: A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

Abstract: A read operation is performed on a memory device in accordance with a pass-through voltage setting that defines a pass-through voltage applied to one or more cells of the memory device during read operations. A number of zero bits read from the memory device based on the read operation are counted and compared with a threshold value. Based on the number of zero bits exceeding the threshold value, the pass-through voltage is increased by adjusting the pass-through voltage setting.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory cells and a memory controller. The memory controller may be configured to control the memory device to generate dummy data based on write data, when a size of the write data is less than a preset size, and to store program data including the write data and the dummy data in selected memory cells among the plurality of memory cells.

Abstract: A storage device includes an accelerator including a first processor, and a storage controller that uses a buffer memory as a working memory and includes a second processor different in type from the first processor. The second processor is configured to establish a first communication path between the first processor and the buffer memory responsive to a request of the first processor, and the first processor is configured to access the buffer memory through the first communication path.