Abstract: A semiconductor apparatus includes a termination voltage terminal, a first pin, a second pin, a first termination circuit and a second termination circuit. The first termination circuit is coupled between the termination voltage terminal and the first pin. The second termination circuit is coupled between the termination voltage terminal and a second pin. Resistance values of the first termination circuit and the second termination circuit may be determined on a basis of distances from the termination voltage terminal to the first pin and the second pin.

Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.

Abstract: The present disclosure provides an off-chip driver (OCD) and an associated DRAM. The OCD operates in a power domain. The power domain works under a minimum system voltage and a maximum system voltage. The OCD is configured for providing a drive current to an output pad. The OCD includes a pull-push circuit. The pull-push circuit is coupled to the output pad. The pull-push circuit includes a current source circuit. The current source circuit includes a VCCS. The VCCS is configured to provide, in response to an operation voltage, an impedance with respect to the output pad, wherein the operation voltage ranges between the minimum system voltage and the maximum system voltage.

Abstract: A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

Abstract: An example device is configured to emit a first light having a first luminous flux and a peak intensity at a first wavelength that is greater than or equal to 400 nanometers (nm) and less than or equal to 480 nm. The first luminous flux is variable and/or the emission of the first light is interrupted one or more times. The device is also configured to emit a second light having a second luminous flux and a peak intensity at a second wavelength that is greater than or equal to 500 nm and less than or equal to 630 nm. The second luminous flux is variable and/or the emission of the second light is interrupted one or more times. The first luminous flux is at a maximum at least during a time at which the second luminous flux is not at a maximum.

Abstract: An example device is configured to emit a first light having a first luminous flux and a peak intensity at a first wavelength that is greater than or equal to 400 nanometers (nm) and less than or equal to 480 nm. The first luminous flux is variable and/or the emission of the first light is interrupted one or more times. The device is also configured to emit a second light having a second luminous flux and a peak intensity at a second wavelength that is greater than or equal to 500 nm and less than or equal to 630 nm. The second luminous flux is variable and/or the emission of the second light is interrupted one or more times. The first luminous flux is at a maximum at least during a time at which the second luminous flux is not at a maximum.

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

Abstract: A solid state lighting SSL assembly comprises an SSL device, a capacitor, a directional conducting device and a supply switch. The capacitor is coupled in parallel with the SSL device. The directional conducting device is coupled between an output terminal of the capacitor and a supply terminal which provides a supply voltage for the SSL assembly. The directional conducting device is configured to conduct in a direction from the output terminal to the supply terminal and to isolate in the opposite direction. The supply switch is coupled between the output terminal and ground. In addition, a method for operating a solid state lighting SSL assembly is proposed.

Abstract: A light-emitting diode (LED) lighting device includes (i) a selector circuit that sequentially and cyclically selects a plurality of LED loads one by one, the plurality of LED loads respectively emitting light as a result of being selected, and (ii) a control circuit that controls the selector circuit to cause an intermediate color to be produced by successively generating frames, each frame being a temporal combination of at least one first cycle period and at least one second cycle period, the at least one first cycle period generating a first mixed emission color, and the at least one second cycle period generating a second mixed emission color different from the first mixed emission color.

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad included in a pad formation area that receives a power voltage; a sub-threshold current reduction circuit (SCRC) included in a peripheral circuit area including a via disposed on a first side of the peripheral circuit area, and a wiring that couples the pad to the via. The SCRC further includes: a voltage line coupled to the via; a logic gate circuit that propagates a signal; an SCRC voltage line coupled to the logic gate circuit; and a SCRC switch disposed in proximity to the via and couples the SCRC voltage line to the voltage line.

Abstract: A circuit to isolate a first circuit node from second circuit node at certain times yet connect the first circuit node and second circuit node at other times. For example, the isolation circuit may isolate a reference node from a system ground during certain phases of operation, but temporarily connect the reference node to the system ground during other phases. An isolation circuit of this disclosure may include a pair of MOSFETs in a back-to-back connection. The MOSFETs may be placed between the two nodes to be isolated. The MOSFETS may be driven by a bipolar junction transistor (BJT). A control signal applied to the BJT emitter controls the operation of the pair of MOSFETs. The isolation or connection from the power supply reference node to system ground may be controlled by applying a HIGH or LOW logic signal to the PNP transistor emitter.

Abstract: A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Abstract: A lighting system, including: light emitting elements; a reset switch operable in a first and second state; non-volatile reset memory configured to record the state of the reset switch when power is provided to the system; a wireless communication system; non-volatile communication memory configured to store default settings and configuration settings; a control system operable, in response to initial power provision to the control system, between: a configured mode when an instantaneous reset switch state matches the recorded state, the configured mode including: connecting the wireless communication system to a remote device based on the configuration settings, receiving instructions from the remote device, and controlling light emitting element operation based on the instructions; and a reset mode when the instantaneous reset switch state differs from the recorded state, the reset mode including: erasing the configuration settings from the communication memory and operating the system based on the default

Abstract: A power and control assembly is disclosed. An LED driver is sized and adapted to fit within a single compartment of an electrical gang box. The driver has a groove or channel, and an electrical element, such as a switch, is sized to fit within the groove.

Abstract: An intelligent light bulb is provided as well as a method, devices and computer program product of configuring such an intelligent light bulb. The intelligent light bulb comprises an LED lighting element and a programmable controller. The programmable controller comprises a memory module having stored therein firmware including instructions for controlling operations of the LED lighting element, where the memory module including a passive memory on which at least a portion of the firmware is stored. The passive memory component of the memory module is responsive to a signal carrying firmware update information received over a wireless communication link from a device external to the intelligent light bulb for causing a firmware update process to be performed to modify the instructions of the firmware based on the update information carried by the signal.

Abstract: An integrated circuit device includes dispatcher circuitry that receives signals from a first number of sources, multiplexes the signals into a single mixed signal in a predetermined order, and transmits the mixed signal to a destination via a mixed signal interface having an arbitrary length and operating at an interface clock frequency equal to a product of a device clock frequency and the first number. A second number of samplers is disposed in series along the mixed signal interface, outputting a sampled mixed signal synchronized to the interface clock. A chain of tracking elements in series, corresponding in number to the second number, outputs a tracking indication separate from the sampled mixed signal. Capture circuitry demultiplexes the sampled mixed signal into a plurality of demultiplexed signals, according to a starting point based on the tracking indication, onto a plurality of signal buses corresponding in number to the first number.

Abstract: Techniques and devices are provided for sensing image data from a scene and activating primary light sources based on information sensed from the scene. Subsets of a plurality of primary light sources may be activated to emit sensing spectrum of light onto a scene. Combined image data may be sensed from the scene while the subsets of the plurality of primary light sources are activated. Reflectance information for the scene may be determined based on the combined image data and combined sensing spectra. Spectrum optimization criteria for the primary light sources may be determined based on the reference information and a desired output parameter provided by a user or determined by a controller. The plurality of primary light sources may be activated to emit a lighting spectrum based on the spectrum optimization criteria.