Abstract: A lighting system, including: light emitting elements; a reset switch operable in a first and second state; non-volatile reset memory configured to record the state of the reset switch when power is provided to the system; a wireless communication system; non-volatile communication memory configured to store default settings and configuration settings; a control system operable, in response to initial power provision to the control system, between: a configured mode when an instantaneous reset switch state matches the recorded state, the configured mode including: connecting the wireless communication system to a remote device based on the configuration settings, receiving instructions from the remote device, and controlling light emitting element operation based on the instructions; and a reset mode when the instantaneous reset switch state differs from the recorded state, the reset mode including: erasing the configuration settings from the communication memory and operating the system based on the default

Abstract: An integrated circuit system includes: a storage element which stores in advance a plurality of pieces of circuit information and startup control circuit information used to configure a startup control logic circuit for selecting circuit information that has not failed in configuring a logic circuit; and an integrated circuit which, at the time of startup or when configuration of the logic circuit based on any of the plurality of pieces of circuit information has failed, configures the startup control logic circuit by reading the startup control circuit information from the storage element, causes the configured startup control logic circuit to select the circuit information that has not failed in configuring the logic circuit, reads the circuit information selected by the startup control logic circuit from the storage element, and configures the logic circuit according to the circuit information.

Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.

Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.

Abstract: A luminaire driver system comprising: a package with input connections for connection to a power supply and output connections for connection to a light emitting device; a predetermined set of circuits arranged in said package; said predetermined set of circuits being adapted to perform a driving functionality of the light emitting device; a receiving means configured for receiving a pluggable module comprising a further circuit, such that the pluggable module can be received from outside of the package, wherein the further circuit is connected to the predetermined set of circuits when the pluggable module is plugged in the receiving means; and connections which are connected to the further circuit when the pluggable module is plugged in the receiving means; wherein the connections are accessible by a user from outside of the package.

Abstract: An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Abstract: A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

Abstract: A qubit includes a superconducting loop interrupted by a plurality of magnetic flux tunneling elements, such as DC SQUIDs, leaving superconducting islands between the elements. An effective transverse magnetic moment is formed by magnetically tuning each element to yield a large tunneling amplitude. The electrical polarization charge on an island is tuned to produce destructive interference between the tunneling amplitudes using the Aharonov-Casher effect, resulting in an effectively zero transverse field. Biasing the charge away from this tuning allows tunneling to resume with a large amplitude. Interrupting the island with a third tunneling path, such as a Josephson junction, permits independently tuning and biasing the two islands that result, enabling effective control of two independent (X and Y) transverse fields.

Abstract: An antenna subsystem of a communication device has an open cavity including an inner opening and lateral and outer sides that define a cavity. The cavity is sized less than required for cavity mode resonance at a millimeter-wave operating frequency. A millimeter-wave antenna element placed at the inner opening of the hollowed section cavity excites evanescent electromagnetic fields in the cavity. A slot antenna is formed in a metallic layer of the outer side of the cavity. A metallic sectioned proximity post has a first section positioned adjacent to and spaced apart from the millimeter-wave antenna element to couple to, and conduct, the evanescent electromagnetic field. The metallic proximity post has a second section positioned adjacent to and spaced apart from the slot antenna to couple at the millimeter-wave operating frequency, enabling re-radiation by the slot antenna.

Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

Abstract: A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.

Abstract: A hybrid of initial time consuming phase of a Single Directional Dijkstra's Algorithm is embodied on an unclocked CMOS logic chip using a parallelized approach with Asynchronous Digital Logic (ADL). The chip includes a a plurality of addressable configurable cells arranged as a multidimensional orthogonal array. The cell array only executes mathematical operations based on a communication between immediately adjacent cells.

Abstract: A line driver circuit is configured to provide a high spurious free dynamic range output and includes first and second output transistors and a control circuit. The first output transistor is controllable to pull an output node to a logic high state, and the second output transistor is controllable to pull the output node to a logic low state. The first control circuit is connected to a control input of the first output transistor and configured to establish a control signal at the control input of the first output transistor while the second output transistor is in a low impedance operating state to reduce an imbalance in turn-on delay between the first output transistor and the second output transistor.

Abstract: Various implementations described herein are directed to an integrated circuit with logic circuitry having one or more components. The integrated circuit may include performance sensing circuitry that provides a performance sensing output associated with detecting variation of switching delays of the one or more components forming the logic circuitry. The integrated circuit may include transient sensing circuitry that receives the performance sensing output and provides a transient sensing output for determining stability of operating conditions of the performance sensing circuitry during one or more sampling periods. The transient sensing circuitry may use a finite state machine (FSM) to sense and classify changes in temporal behavior of the transient sensing output.

Abstract: Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.

Abstract: The present disclosure provides an intelligent lighting control system. The lighting control system transmits a first wireless signal from a first light control module to a second light control module at a launch time. The first wireless signal is detected at the second light control module. A second wireless signal is transmitted from the second light control module to the first light control module in response to detecting receipt of the first wireless signal. The lighting control system detects receipt of the second wireless signal at the first light control module. A receipt time of the detection of the second wireless signal is recorded. The lighting control system determines a time of flight measured from the launch time to the receipt time.

Abstract: The present disclosure provides an intelligent lighting control system configured for customization based user detection. A lighting control system includes a module housing, a graphical user interface, and a switch control circuit including a processor configured to modulate the flow of electrical energy to a lighting circuit via a dimmer circuit to produce a plurality of lighting scenes. The processor is configured to identify a proximate device identification, compare the identified device with one or more registered devices saved in a dataset, select a user profile, if the identified device corresponds to one of the one or more registered devices saved in the dataset. The processor is configured to cause a change in at least one of a scene selection protocol for selecting at least one lighting scene from the plurality of lighting scenes based on the user profile selected and a display setting of the graphical user interface.

Abstract: An example of a lighting system includes intelligent lighting devices, each of which includes a light source, a communication interface and a processor coupled to control the light source. In such a system, at least one of the lighting devices includes a user input sensor to detect user activity related to user inputs without requiring physical contact of the user; and at least one of the lighting devices includes an output component to provide information output to the user. One or more of the processors in the intelligent lighting devices are further configured to process user inputs detected by the user input sensor, control lighting and control output to a user via the output component so as to implement an interactive user interface for the system, for example, to facilitate user control of lighting operations of the system and/or to act as a user interface portal for other services.