Abstract: A source-coupled logic (SCL) gate configured to reduce power supply noise generation and reduce DC power consumption by adjusting a bias current to deliver only the performance level required for a given application. The SCL gate circuit arrangement includes a current mirror circuit with transistors configured as pull-up transistors. The pull-up transistors set the logical HIGH voltage level. The SCL gate circuit may also include voltage limiting devices configured to set the logical LOW voltage level. The current mirror circuit and the voltage limiting devices allow the SCL gate to receive a bias current supplied a bias circuit that is less complex than bias circuitry used by other examples of SCL circuitry. Adjusting the bias current delivers the desired performance with the commensurate reduction in power consumption.

Abstract: An antenna device includes antenna units, transmission lines and switching circuits. The antenna units are used to be operated in a directional mode or an omni-directional mode. The transmission lines are coupled to the antenna units. The switching circuits are coupled to the respective transmission lines, and are used for selectively connecting the transmission lines according to control signals. At least one transmission line is disconnected when the antenna units are operated in the directional mode. All the transmission lines are connected when the antenna units are operated in the omni-directional mode.

Abstract: A driver circuit that includes an input side including a power input circuit and an output side including a light emitting diode (LED) output current circuit. The output side of the driver circuit includes an output smoothing capacitor for controlling flicker percentage. A light emitting diode (LED) power supply circuit is present between the input side and the output side for controlling current from the AC power input circuit to the light emitting diode (LED) output current circuit. The LED power supply circuit includes at least two linear current regulators that are connected in parallel. The circuit also includes a controller circuit including a controller for signaling the light emitting diode (LED) power supply to control current to the light emitting diode (LED) output current circuit to provide a lighting characteristic.

Abstract: An apparatus may include a substrate assembly having a first side and a second side. The apparatus may further include a waveguide antenna element positioned on the first side of the substrate assembly. The apparatus may also include a first reference ground plane positioned on the first side of the substrate assembly. The apparatus may include a microstrip line positioned within the substrate assembly. The apparatus may further include a stripline positioned within the substrate assembly and electrically coupled to the microstrip line, the first reference ground plane overlapping the stripline. The apparatus may also include a second reference ground plane positioned on the second side of the substrate assembly and overlapping both the microstrip line and the stripline. The apparatus may include a stripline antenna element positioned on the second side of the substrate assembly and enclosed by the second reference ground plane.

Abstract: A communication device provides an elongate antenna element having a first and a second end separated by an aperture. A transceiver is electrically grounded to a ground plane and communicatively coupled via an antenna feed to the elongate antenna element. A first conductor is electrically attached to a first edge of the ground plane. An antenna switching controller selectively actuates the aperture switch to be in one of the open and closed positions based on whether the communication device is positioned on a body. The open position electrically isolates (a) the first end of the elongate antenna element; (b) the second end of the elongate antenna element; and (c) the first conductor. The closed position electrically couples: (a) the first end of the elongate antenna element; (b) the second end of the elongate antenna element; and (c) the first conductor.

Abstract: Examples disclosed herein relate to a method comprising determining, by a control state machine running on a control module, a state for a plurality of modules communicatively coupled to the control module, wherein each module has a corresponding state machine that publishes state information into a centralized database. The method may include publishing, by the control state machine, the target state for each module in the plurality of modules, into the centralized database, wherein each target state is associated with a set of actions to enable the module to achieve the target state. The method may also include determining, by the control state machine, that each module in the plurality of modules has published its new state to the database and initializing, by the control state machine, a process related to at least one module in the plurality of modules.

Abstract: An antenna includes: a first substrate and a second substrate; a first antenna electrode is disposed on a side of the first substrate away from the second substrate; a second antenna electrode is disposed on a side of the second substrate away from the first substrate and a microstrip line is disposed on a side of the second substrate close to the first substrate; a liquid crystal layer is disposed between the first substrate and the second substrate; at least one drive electrode assembly is disposed between the first substrate and the second substrate. The at least one drive electrode assembly is configured to achieve impedance matching of the antenna by controlling liquid crystal molecules of the liquid crystal layer to deflect.

Abstract: A low-power low-setup integrated clock gating (ICG) cell is disclosed. The disclosed ICG cell includes a NOR gate configured to receive an enable (E) signal and a test enable (SE) signal, and to output an EN signal. The ICG cell may include a complex gate configured to receive the EN signal and a clock (CK) signal, and to output a latched enable (ELAT) signal. The ICG cell may further include a NAND gate configured to receive the ELAT signal and the CK signal, and to output an inverted enabled clock (ECKN) signal. The ICG cell may further include an inverter configured to receive the ECKN signal from the NAND gate, and to output an enable clock (ECK) signal.

Abstract: Described is soft error tolerant flip-flop which comprises hardened sequential elements to reduce latch soft error rate. The flip-flop may include a master latch; and a slave latch coupled to the master latch, wherein only one of the master or slave latch of the flip-flop comprises hardened latch circuitry. For example, only the master latch comprises the hardened latch circuitry.

Abstract: A wall-mounted keypad may include a light detector circuit located inside the keypad that is configured to measure an ambient light level in a space. The light detector circuit may receive ambient light through an aperture that is hidden from view by the keypad. The keypad may include a reflector for directing ambient light onto the light detector circuit. The keypad may include an enclosure that houses the light detector circuit. The enclosure may define a recess that exposes at least a portion of the light detector circuit. The enclosure may include a reflector that may focus ambient light received through the aperture onto the light detector circuit. The keypad may include a control circuit that may be configured to illuminate the indicia of respective buttons of the control device in response to actuations of the one or more buttons, in accordance with the measured ambient light level.

Abstract: A convertible mobile device includes an upper cover, a base, a hinge element, a supporting element, an antenna structure, and a cover element. The hinge element is connected between the upper cover and the base, so that the convertible mobile device can flip over and operate in a notebook mode or a tablet mode. The antenna structure is disposed on the supporting element. The antenna structure includes a first radiation element and a second radiation element. One of the first radiation element and the second radiation element has a positive feeding point, and the other of the first radiation element and the second radiation element has a negative feeding point. A coupling gap is formed between the first radiation element and the second radiation element. The cover element covers the supporting element, the antenna structure, and at least a portion of the hinge element.

Abstract: An antenna module and a mobile device are provided. The antenna module includes a radiator formed on a surface of the plastic rear housing facing the back cover, and a feed point, a first ground point, and a second ground point that are disposed on the motherboard. The antenna module further includes a matching network, a first tuning switch, and a second tuning switch. The feed point is connected to the radiator through the matching network. The first ground point is connected to the radiator through the first tuning switch. The second ground point is connected to the radiator through the second tuning switch. The surface of the plastic rear housing facing the back cover includes a first shaping zone for shaping the radiator and a second zone other than the first shaping zone, and the radiator completely covers the first shaping zone.

Abstract: Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals.

Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.

Abstract: A reflector system includes a hoop assembly formed of a plurality of link members extending between a plurality of hinge bodies. The link members have an expanded configuration wherein the link members define a circumferential hoop having a central hoop axis. A collapsible mesh reflector surface is secured to the hoop such that when the hoop assembly is in the expanded configuration, the reflector surface is expanded to a shape that is intended to concentrate RF energy. A mast assembly includes an extendible boom aligned along a central boom axis. The hoop assembly is secured by a plurality of cords relative to the boom such that when the hoop is expanded, a central hoop axis is laterally offset a predetermined distance from the central boom axis.

Abstract: The individual configuration of beacons in lighting systems is to be simplified. Therefore, a lighting system with a lighting device and a beacon arranged in or at the lighting device is provided. The lighting system comprises a sensor device for acquiring an environmental parameter relating to an environment of the lighting system. Moreover, the beacon is formed to automatically configure itself based on the environmental parameter.

Abstract: A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.

Abstract: A method, system, and apparatus for setting an on-chip password is provided. In an embodiment, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.

Abstract: Provided is a variable electronic apparatus including a memory unit, a processing unit and a programmable logic gate device. The memory unit stores configuration data. The processing unit reads the configuration data from the memory unit and determines at least one control mode based on the configuration data. The programmable logic gate device includes a plurality of function modules and at least one switching unit. When the control mode includes a function module selecting mode and a signal line switching mode, the processing unit selects or activates the function modules of the programmable logic gate device based on the function module selecting mode, and the switching unit of the programmable logic gate device dynamically modifies or adaptably adjusts a bus of the function module selected by the processing unit and a corresponding external signal line based on the signal line switching mode.

Abstract: A coaxial cable may include a center conductor having a first resistance, and dielectric material may be formed around the center conductor. An outer conductor may be coaxially formed around the center conductor and the dielectric material. The outer conductor may have a second resistance substantially equal to the first resistance, and at least one slot may be formed through the outer conductor. A jacket may be formed around the outer conductor.