Patents Examined by Daniel F McMahon
  • Patent number: 10601450
    Abstract: Techniques are described to address run-time issues and other considerations of data structure reorganization operations executed while decoding a polar code. A receiving entity (e.g., a user equipment or a base station) partitions an array, or other data structure, into sections. The array is used during a list decoding operation of a polar code. As the array is populated with path elements for candidate paths, each section is organized and a permutation pattern is calculated for each section. Upon identifying a section reorganization event, the array or subsections of the array are reorganized according the permutation patterns determined for each section.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jamie Menjay Lin, Yang Yang, Gabi Sarkis, Rotem Cooper, John Edward Smee
  • Patent number: 10593419
    Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: March 17, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Steven Lee Gregor, Puneet Arora, Norman Robert Card
  • Patent number: 10585141
    Abstract: A pin connection testing system for connector, and a method thereof are disclosed. In the pin connection testing system, a JTAG instruction is used to control a PLD, to drive the demultiplexer to transmit each to-be-tested signal, which is from the connector, to a first line or a second line; and, when the to-be-tested signal is transmitted to the first line, the to-be-tested signal is converted from analog to digital and encoded, and then transmitted to I/O pins of the PLD for reading; and, when the JTAG command is transmitted to the second line, the PLD reads the statuses of the I/O pins electrically connected to the second line; and then the PLD generates a test result according to the to-be-tested signals and the read I/O pins. Therefore, the technical effect of improving convenience in testing the connection status of the connector can be achieved.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 10, 2020
    Assignees: Inventec (Pudong) Technology Corporation, Inventec Corporation
    Inventor: Ping Song
  • Patent number: 10585750
    Abstract: An embodiment of the invention includes a method, computer program product and system for object data storage. The embodiment includes receiving a data object for storage within a set of dispersed storage units. The data object includes object data and associated object metadata. The embodiment includes replicating the object metadata of the received data object to create more than one copy of the associated object metadata. The embodiment includes encoding the received data object to produce a plurality of data slices. The encoding includes dispersed storage error encoding. The embodiment includes appending a copy of the associated object metadata to each data slice within the plurality of data slices. The embodiment includes transmitting the plurality of data slices to the set of dispersed storage units.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gregory R. Dhuse, Adam M. Gray, Ravi V. Khadiwala, Wesley B. Leggette, Jason K. Resch
  • Patent number: 10585732
    Abstract: Systems and methods are disclosed for categorizing error types encountered in data access operations based on bit information from a data segment. An example apparatus includes a circuit configured to perform error recovery for one or more data segments including determining an error recovery operation of a plurality of error recovery operations to perform based on bit information of the one or more data segments. The example circuit also performs the determined error recovery operation.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 10, 2020
    Assignee: Seagate Technology LLC
    Inventors: Seokhun Jeon, MinGyeong Son, Seung Youl Jeong
  • Patent number: 10581555
    Abstract: An information processing device is provided that includes a receiver to receive information from another information processing device that mutually communicates the information and a processor to process the information received by the receiver. The receiver detects occurrence of a burst error in the received information, sequentially writes the received information in a first memory, stops the writing of the information to the first memory based on detection of the burst error, shuts off transmission of the information received from the another information processing device based on a reproducing instruction, and transmits the information read from the first memory.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Maeda, Atsushi Miki
  • Patent number: 10574397
    Abstract: An information processing apparatus including a control unit that performs control for adding, to request information for requesting a different apparatus for a confirmation response to a plurality of data transmitted to the different apparatus, notification information. The notification information is information regarding at least sequence numbers other than a start sequence number from among sequence numbers corresponding to the plurality of data. Further, the control unit transmits the request information, to which the notification information is added, to the different apparatus.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 25, 2020
    Assignee: SONY CORPORATION
    Inventors: Shigeru Sugaya, Eisuke Sakai
  • Patent number: 10567102
    Abstract: Methods and systems for enabling recovery of lost packets transmitted over a communication network. In one embodiment, a device includes a processor and a transmitter. The processor is configured to calculate a row parity packet (RPP) and a diagonal parity packet (DPP) for n packets. Each of the RPP, the DPP, and the n packets comprises n segments. The processor utilizes each packet, from among the n packets, to update parity values in the RPP and the DPP in such a way that each segment in the packet is used to update one segment in the RPP and at most one segment in DPP. The transmitter transmits the n packets, the RPP, and the DPP over the communication network. Receiving a subset of n members of a set comprising: the RPP, the DPP, and the n packets, enables recovery of two lost packets.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: February 18, 2020
    Assignee: Valens Semiconductor Ltd.
    Inventors: Shai Stein, Eran Rippel
  • Patent number: 10560116
    Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 11, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kumar Chhabra, Rohit Halba, Shashi Kumar Shaw, Shrikrishna Nana Mehetre
  • Patent number: 10554225
    Abstract: A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yiming Chen, Anantha Raman Krishnan
  • Patent number: 10554339
    Abstract: A technique for managing transfer of data frames having a pre-determined mutual order is presented. Each data frame contains an order indicator, for example a sequence number, indicative of the position of the data frame in the pre-determined mutual order. A transmitting end provides each data frame with a satisfaction indicator that indicates whether acknowledgement about reception of earlier transmitted data frames is expected from a receiving end. When the satisfaction indicator of a data frame indicates that no acknowledgement is expected, the receiving end knows that the data frame can be treated as a beginning of a received data flow when checking the integrity of the received data flow on the basis of the order indicators. Thus, there is no need to establish a logical connection between the transmitting and receiving ends prior to the transfer of the data frames.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: February 4, 2020
    Inventors: Ville Hallivuori, Juhamatti Kuusisaari
  • Patent number: 10552261
    Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Hashizume, Naoya Fujita, Shunya Nagata, Yoshisato Yokoyama, Katsumi Shinbo, Kouji Satou
  • Patent number: 10554221
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10541770
    Abstract: Methods and systems that enable recovery lost packets that were transmitted over a communication network. In one embodiment, a device includes a receiver and a processor. The receiver receives n packets that belong to a set comprising n+2 packets transmitted over the communication network, where the set includes: n data packets, a row parity packet (RPP), and a diagonal parity packet (DPP). Each received packet comprises n segments. Each segment of the RPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet from among the n data packets. Each segment of the DPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet selected from a group comprising the n data packets and the RPP. The processor may utilize the received packets to recover two lost packets.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Valens Semiconductor Ltd.
    Inventors: Shai Stein, Eran Rippel
  • Patent number: 10540315
    Abstract: A computing system is provided. The computing system includes a host device and a plurality of interface devices. The plurality of interface devices is configured to communicate with the host device through a host bus. Each of the plurality of interface devices is configured to perform an interfacing operation between the host device and a memory device. The interfacing operation includes a serial interfacing operation and a parallel interfacing operation.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyung Seob Bae
  • Patent number: 10535418
    Abstract: A memory device including a memory cell region having a normal cell array and a redundant cell array, a fuse unit having a plurality of fuse sets corresponding to the redundant cell array and which is used for programming an address of a repair target memory cell of the normal cell array and a deciding unit which determines fuse sets that are used in a first operation mode according to a control signal.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Jung-Taek You
  • Patent number: 10530397
    Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui, Timothy David Anderson
  • Patent number: 10521299
    Abstract: Embodiments of the present disclosure relate to method and apparatus for data protection. For example, there is provided a computer-implemented method. According to the computer-implemented method, it only needs to read the changed data to be protected rather than the entire data to be protected during the procedure of generating a redundant data portion for the changed data to be protected.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 31, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ronnie Yu Cai, Ao Sun, Gary Jialei Wu, Lu Lei, Chen Wang
  • Patent number: 10514981
    Abstract: A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsik Kim, Tae-Hwan Kim
  • Patent number: 10511405
    Abstract: Resource mapping and coding schemes to handle bursty interference are disclosed that provide for spreading the modulated symbols for one or more transmission code words over more symbols in the time-frequency transmission stream. Certain aspects allow for the modulated symbols to be based on bits from more than one code word. Other aspects also provide for re-mapping code word transmission sequences for re-transmissions based on the number of re-transmissions requested by the receiver. Additional aspects provide for layered coding that uses a lower fixed-size constellation to encode/decode transmissions in a layered manner in order to achieve a larger-size constellation encoding. The layered encoding process allows the transmitter and receiver to use different coding rates for each coding layer. The layered encoding process also allows interference from neighboring cells to be canceled without knowledge of the actual constellation used to code the interfering neighboring signal.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: December 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Srinivas Yerramalli, Tao Luo, Durga Prasad Malladi, Naga Bhushan, Yongbin Wei, Tingfang Ji, Aleksandar Damnjanovic, Wanshi Chen