Abstract: Systems and methods are disclosed for an improved utilization of parity within a data storage device, and manufacturing methods thereof. In some embodiments, a data storage device can implement an improved codeword redundancy process that can be utilized for data storage locations which were not previously scanned for defects. In some embodiments, a data storage device can implement an improved codeword redundancy process to store write data to a data storage location without having to perform a read operation prior to storing the write data to the storage location. The improved codeword redundancy process can include various methods of storing or updating an outer code codeword for the data to be stored.

Abstract: Disclosed are devices and methods for improved operations of a memory device. In one embodiment, a method is disclosed comprising periodically recording memory statistics of a dynamic random-access memory in a device, while the device is in a power on state; detecting a command to enter a standby state; analyzing the memory statistics to determine whether a health check should be performed; powering down the device when determining that the health check should be performed; and placing the device in standby mode when determining that the health check should not be performed.

Abstract: A system includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration. The first configuration includes a first set of control settings for reading a block of the memory array during the first attempt. The operations further include determining that the first attempt has failed, and, in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed. Causing the automatic chip initialization retry process to be performed includes causing a second attempt of the chip initialization process to be performed using a second configuration. The second configuration includes a second set of control settings different from the first set of control settings for reading the block during the second attempt.

Abstract: A distribution statistic is generated for a data block of a memory component based on a reliability statistic for memory cells sampled in the data block. The distribution statistic is indicative of at least one of a uniformity or a non-uniformity of read disturb stress on the sampled memory cells. At least a subset of the data block is relocated to another data block of the memory component in view of the distribution statistic.

Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.

Abstract: A storage device reclassification system includes a storage device reclassification subsystem coupled to a storage device that has a NAND storage subsystem and that is configured to perform first storage operations associated with a first storage device classification. The storage device reclassification subsystem performs testing operations on the NAND storage subsystem and, based on the testing operations, identifies at least one reduced capability of the NAND storage subsystem. Based on the at least one reduced capability of the NAND storage subsystem, the storage device reclassification subsystem determines at least one storage device operation modification and performs the at least one storage device operation modification on the storage device in order to configure the storage device to perform second storage operations that are different than the first storage operations and that are associated with a second storage device classification that is different than the first storage device classification.

Abstract: Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.

Abstract: A method of performing partial redundant array of independent disks (RAID) stripe parity calculations is disclosed. The method includes receiving a last portion of a RAID stripe among multiple portions of the RAID stripe, all portions for a successful write of the RAID stripe being previously received except for the last portion. The method also includes calculating a parity value based on the last portion of the RAID stripe and a previous parity value without calculating the parity value using a previous portion of the RAID stripe. The method further includes writing of the RAID stripe.

Abstract: An integrated circuit is provided that comprise a receive unit to be tested for receiving an input signal and storing the input signal at a predetermined point of time. Additionally, it comprises a processor for applying an error correction to the received input signal, for comparing the error corrected signal with an expectation value and for outputting an error message when the filtered input signal does not correspond to the expectation value. A power source supplies the receive unit to be tested with an adjustable voltage and/or and adjustable current. An adjustment unit varies the predetermined point in time and the adjustable voltage respectively the adjustable current.

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

Abstract: A semiconductor memory includes storage arrays, at least one verification module and gating circuits. Each verification module corresponds to multiple storage arrays. The verification module is configured to verify whether an error occurs in data information of the corresponding storage arrays. Each verification module is connected to a group of global data buses. The gating circuits are respectively connected to the storage arrays and the global data buses, and the gating circuits are configured to control on and off of a data transmission path connecting the global data buses to the storage arrays.

Abstract: A testing and verification system for an equivalent physical configuration of an in-flight entertainment and communications system with one or more hardware components includes a virtual machine manager. One or more virtual machines each including a hardware abstraction layer is instantiated by the virtual machine manager according to simulated hardware component definitions corresponding to the equivalent physical configuration of the hardware components. The virtual machines are in communication with each other over virtual network connections. A test interface to the one or more virtual machines generate test inputs to target software applications installed on the virtual machines. A display interface is connected to the virtual machines, with results from the execution of the target software applications responsive to the test inputs are output thereto.

Abstract: A signal receiving method include: demodulating a signal received from a transmitting apparatus to generate values based on 1024-quadrature amplitude modulation (QAM); splitting the values into a plurality of groups; deinterleaving the plurality of groups based on a preset interleaving order; and decoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800, wherein the plurality of groups are deinterleaved based on a predetermined equation.

Abstract: An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include decoding the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

Abstract: A cluster of one or more computing devices is operably coupled to a plurality of storage devices. Each computing device in the cluster comprises a frontend and a backend. The backend comprises a plurality of buckets. Each bucket is operable to build a failure-protected stipe that spans two or more of the plurality of the storage devices. A file system comprises one or more failure-protected stipes. A client other than the one or more computing devices in the cluster is operable to access at least a portion of the file system via a stateless mount string comprising a cryptographically-signed key.

Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.

Abstract: A data storage device includes a non-volatile memory and a data storage controller. The data storage controller is configured to generate first XOR parities based on first data of a first metablock of the non-volatile memory and store the first XOR parities in a second metablock of the non-volatile memory. The data storage controller is also configured to generate second XOR parities corresponding to second data of the second metablock. The second data includes two or more XOR parities of the first XOR parities. The data storage controller is further configured to store the second parities in a reserved portion of the first metablock.

Abstract: A method includes generating an ECC encoded output data by executing an ECC-Space operation using an ECC encoded first data from a memory as a first operand and an ECC encoded second data from the memory as a second operand. The ECC-Space operation is translated from a two operands operation that is operative to transform a first data and a second data into a third data. A result of encoding the first data is the ECC encoded first data and a result of encoding the second data is the ECC encoded second data if the first data and the second data are encoded with an ECC algorithm. The method also includes storing the ECC encoded output data to the memory. The ECC encoded output data is identical to a result of encoding the third data if the third data is encoded with the ECC algorithm.