Patents Examined by Daniel Luke
  • Patent number: 11011508
    Abstract: An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Robert Callaghan Taft, Alan Erik Segervall, Muhammad Yusuf Ali
  • Patent number: 11011579
    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Samuele Sciarrillo
  • Patent number: 10978388
    Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari Prasad Amanapu, Prasad Bhosale, Nicholas V. LiCausi, Lars W. Liebmann, James J. McMahon, Cornelius Brown Peethala, Michael Rizzolo
  • Patent number: 10964639
    Abstract: An integrated circuit (IC) includes a via stack, and the via stack includes via arrays including a plurality of vias at the same level. A plurality of vias of a via array are arranged at intersections between tracks of adjacent conductive layers and arranged along a central line between the tracks. Also, a via overlap extends parallel to tracks of a conductive layer. Thus, the number of tracks sacrificed by the via array may be reduced, and the IC may have enhanced performance and a reduced area due to improved routability.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 30, 2021
    Inventor: Yong-durk Kim
  • Patent number: 10950573
    Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Clement J. Fortin, Christopher D. Muzzy, Krishna R. Tunga, Thomas Weiss
  • Patent number: 10916427
    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
  • Patent number: 10916519
    Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 10910331
    Abstract: A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: February 2, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 10910459
    Abstract: A display panel is provided having a transparent region, a display area surrounding the transparent region, and a non-display area surrounding the display area, and the display panel includes: at least one binding pin; at least one signal line only located within the display area and not located within the transparent region; at least one connection line located within the non-display region; and glass cement located within the non-display region. The signal lines include a first signal line and a second signal line, and the first signal line and the at least one binding pin are respectively located at two sides of the transparent region; the first signal line is electrically connected to the at least one connection line; and at least a part of the at least one connection line overlaps with the glass cement. The display panel is used for image display.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 2, 2021
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yujiao Liang, Mengmeng Zhang, Di Zhu, Tao Peng, Yue Li, Yana Gao, Xingyao Zhou
  • Patent number: 10903116
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Patent number: 10896870
    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate, a first metal wiring and a second metal wiring disposed in the interlayer insulating layer, the first and second wirings spaced apart from each other in a first direction, the first and second wirings extending to a second direction perpendicular to the first direction, an air gap formed in the interlayer insulating layer between the first metal wiring and the second metal wiring, and spaced apart from a sidewall of the first metal wiring and a sidewall of the second metal wiring, and a capping layer disposed on the interlayer insulating layer, the capping layer covering the first metal wiring, the second metal wiring, and the air gap, wherein the air gap is disposed at a first distance from the first metal wiring in the first direction and at a second distance from the second metal wiring in the first direction, and wherein the first and second distances are the same.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hong Park, Woo Jin Lee
  • Patent number: 10867789
    Abstract: A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Kuang-Yuan Hsu
  • Patent number: 10854675
    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Samuele Sciarrillo
  • Patent number: 10804425
    Abstract: A growth substrate including micro-light emitting diode (LED) chips and a method of manufacturing a light emitting diode display using the growth substrate are disclosed. The growth substrate includes LED chips. The LED chips are divided into n groups each including p LED chips, where each of the n and p is an integer equal to or greater than 2. At least two of the n groups are adjacent to each other. Each of the n includes a first LED chip having a directionality toward a first direction and a second LED chip having a directionality toward a second direction different from the first direction.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 13, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Joonkwon Moon, Hwankuk Yuh, Taesu Oh
  • Patent number: 10804439
    Abstract: A method produces a plurality of conversion elements including: A) providing a first carrier; B) applying a first element to the first carrier using a first application technique, the first element including a conversion material, the first application technique being different from compression molding; C) applying a second element to the first carrier by a second application technique, the second element including quantum dots, the quantum dots being introduced into a matrix material and being different from the conversion material, the second application technique being molding or compression molding; D) hardening of the matrix material; E) optionally, rearranging the arrangement produced according to step D) to a second carrier; and F) separating so that a plurality of conversion elements are generated.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 13, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Pindl, Martin Brandl
  • Patent number: 10796917
    Abstract: A semiconductor device includes: a first semiconductor layer formed, on a substrate, of a nitride semiconductor; a second semiconductor layer formed, on the first semiconductor layer, of a nitride semiconductor; a source electrode formed on the second semiconductor layer; a drain electrode formed on the second semiconductor layer; a metal oxide film formed, between the source electrode and the drain electrode, on the second semiconductor layer; and a gate electrode formed on the metal oxide film. The metal oxide film includes AlOx and InOx. AlOx/InOx in the metal oxide film is greater than or equal to 3.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: October 6, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Naoya Okamoto
  • Patent number: 10784122
    Abstract: A method of producing an electroconductive substrate including a base material, and an electroconductive pattern disposed on one main surface side of the base material includes: a step of forming a trench including a bottom surface to which a foundation layer is exposed, and a lateral surface which includes a surface of a trench formation layer, according to an imprint method; and a step of forming an electroconductive pattern layer by growing metal plating from the foundation layer which is exposed to the bottom surface of the trench.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 22, 2020
    Assignee: TDK CORPORATION
    Inventors: Takashi Daitoku, Susumu Taniguchi, Akiko Seki, Atsushi Sato, Yuhei Horikawa, Makoto Orikasa, Hisayuki Abe
  • Patent number: 10763448
    Abstract: This application relates to an OLED device, a manufacturing method thereof, and a display device. The OLED device includes a light emitting unit between an anode and a cathode. The light-emitting unit includes: a first carrier function layer for migration of first carriers, the first carrier function layer including a first material layer; a second carrier function layer for migration of second carriers having a polarity different from that of the first carriers, the second carrier function layer including a second material layer; a light emitting layer between the first material layer and the second material layer, the light emitting layer including a luminescent material; a first buffer layer between the light emitting layer and the first material layer. The first buffer layer is a mixed layer containing the luminescent material and the first material.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 1, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhiqiang Jiao
  • Patent number: 10732307
    Abstract: A method for producing a device for detecting flux of neutrons with parameters in predetermined ranges, including: one phase of determining parameters, including: simulating penetration of a flux of incident neutrons with parameters in the predetermined ranges through a modelled stack including in succession and in order at least: one first electrode; one substrate including: a first layer; and a second layer; and one second electrode; and simulating at least one defect peak created in the first layer by vacancies and/or ionization of the particles generated by collisions between neutrons of the flux of incident neutrons and atoms of the second dopant species; and identifying depth of the defect peak closest the interface between the first and second layers of the modelled stack.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 4, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITE D'AIX-MARSEILLE
    Inventors: Laurent Ottaviani, Vanessa Vervisch, Fatima Issa, Abdallah Lyoussi
  • Patent number: 10707075
    Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Masashi Sakai, Yasuhiro Kimura, Yoichiro Mitani, Takashi Kanazawa