Abstract: The present disclosure relates to a semiconductor structure including a superlattice with repeating unit cells of a narrow bandgap (NBG) layer and a wide bandgap (WBG) layer. The NBG and WBG layers include an NBG and a WBG polar semiconductor material, respectively. An energy barrier region is in contact with the superlattice, including a total of N layers of alternating the WBG and NBG polar semiconductor materials, wherein a total thickness of the energy barrier region is equal to a thickness of N/2 unit cells of the superlattice, and wherein N is an even number greater than or equal to 4. Layers of the N layers of the energy barrier region, either WBG layers or NBG layers, are both thicker and thinner than a corresponding layer (either WBG or NBG) of the unit cell of the superlattice to form the energy barrier.

Abstract: A display panel, a display device, and a method for repairing a display panel. The display panel includes: a substrate; a driving device layer disposed on the substrate; a light-emitting structure disposed on a side of the driving device layer away from the substrate. The light-emitting structure includes two or more first electrodes and light-emitting function structures respectively disposed at a side of the first electrodes away from the substrate and spaced apart, the two or more first electrodes are spaced apart and connected to each other by a first wire, and the first wire is located between two adjacent first electrodes.

Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.

Abstract: A bonded structure and a method of forming such a bonded structure are disclosed. The bonded structure can include a first element and a second element. The first element has a first bonding surface including a first nonconductive material and a plurality of first contact pads. The first contact pads are electrically connected to one or more first microelectronic devices in the first element. The second element has a second bonding surface including a second nonconductive material and a plurality of second contact pads. The second contact pads are electrically connected to one or more second microelectronic devices in the second element. The second bonding surface is directly bonded to the first bonding surface without an intervening adhesive to form a bonding interface, and one or more first contact pads is omitted from the first microelectronic element to alter the functionality of the bonded structure.

Abstract: A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

Abstract: A method for manufacturing a semiconductor structure includes: forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines; forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion; and forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a structure with an isolated well and methods of manufacture. The structure includes: a floating well of a first dopant type within a semiconductor substrate; a second well of a second dopant type within the floating well of the first dopant type; a reverse bias diode at a junction between the floating well and the semiconductor substrate; and a forward bias diode at a junction between the floating well and the second well.

Abstract: A semiconductor pattern is provided in the present invention, including a first line extending to one end in a first direction and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width is gradually increased to a maximum width toward the end and gradually converged to form the rounding feature.

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first interlayer insulating layer, a lower wiring disposed inside the first interlayer insulating layer, an etching stop layer which includes first to third layers sequentially stacked on the first interlayer insulating layer, a second interlayer insulating layer disposed on the etching stop layer, and a via which penetrates the second interlayer insulating layer and the etching stop layer, the via is connected to the lower wiring, the via includes a first side wall that is in contact with the second layer, and a second side wall that is in contact with the second interlayer insulating layer, the via includes a first protrusion protruding in a horizontal direction from the first side wall inside the first layer, and a second protrusion protruding in the horizontal direction from the first side wall inside the third layer.

Abstract: An interconnection structure is provided to include an interlayer dielectric (ILD) layer that is disposed over a substrate, a metal via that is disposed in the ILD layer, and a metal wire that is disposed over the metal via in the ILD layer and that is electrically connected to the metal via. The ILD layer includes silicon carbon nitride.

Abstract: A method of forming a structure on a substrate that includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer to a nitrogen-containing gas to inhibit growth of the nucleation layer at narrow points within the at least one opening. The method includes exposing the at least one opening of the substrate to the tungsten-containing precursor gas to form a fill layer over the nucleation layer within the at least one opening. The method includes exposing the at least one opening to a molybdenum-containing gas to remove a tungsten nitride layer from the tungsten fill layer.

Abstract: A blank package for mimicking an electronic component package comprises a body and a plurality of conductive pads. The body is formed from generally transparent electrically insulating material and has a top surface, a bottom surface, and a plurality of side surfaces. The bottom surface has a shape and dimensions that are similar to a bottom surface of the electronic component package. The conductive pads are formed from electrically conductive material and attached to the body, with each conductive pad corresponding to a successive one of the conductive pads of the electronic component package. Each conductive pad has features that are similar to features of the corresponding conductive pad of the electronic component package.

Abstract: Interconnect wire structures and techniques for fabrication thereof with uniform line profile and height are provided. In one aspect, a structure is provided that includes: a wafer; a first interlayer dielectric disposed on the wafer; a second interlayer dielectric disposed on the first interlayer dielectric; and an interconnect wire(s) embedded in the first interlayer dielectric and the second interlayer dielectric, where a first portion of a top half of the interconnect wire(s) has vertical sidewalls, and where a second portion of the top half of the interconnect wire(s) and a bottom half of the interconnect wire(s) have flared sidewalls. A first barrier layer and a (potentially different) second barrier layer can separate the bottom half and top half of the interconnect wire(s) from the first and second interlayer dielectrics. A method for forming the interconnect wire(s) is also provided.

Abstract: A method for forming a semiconductor structure includes providing a substrate with an opening in or on the substrate. The method further includes conformally forming a barrier layer in the opening and on the substrate and performing an implantation process to implant a dopant into the barrier layer. The method further includes conformally forming a capping layer on the barrier layer and performing an annealing process, such that the dopant diffuses into the grain boundary of the barrier layer. The method further includes removing the capping layer and filling the opening with a conductive material.

Abstract: An interconnection structure includes a conductive feature disposed in a first dielectric material, a first etch stop layer disposed over the first dielectric material, a second dielectric material disposed on the first etch stop layer, a conductive via extending through the second dielectric material and the first etch stop layer and in contact with at least a portion of the conductive feature, a first barrier layer disposed between the second dielectric material and the conductive via, a first liner disposed between and in contact with the first barrier layer and the conductive via, a third dielectric material disposed over the second dielectric material, a conductive line disposed in the third dielectric material and in direct contact with the conductive via, a second barrier layer disposed on the second dielectric material and in contact with the first barrier layer and the conductive line, and a second liner disposed between and in contact with the second barrier layer and the conductive line, wherein th

Abstract: Proposed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same for positioning the upper end of an air gap formed in a DTI region at a relatively deep position in the DTI region by forming the bottom of the upper region of the DTI region at a deeper position in a substrate compared to the bottom of a STI region.

Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.

Abstract: A method of forming a semiconductor structure and a semiconductor structure are provided. The method of forming the semiconductor structure includes: providing a base, where the base includes a first dielectric layer and pads arranged at intervals in the first dielectric layer; forming a dielectric structure, where the dielectric structure exposes the pad and part of the first dielectric layer; forming an insulating structure, where the insulating structure is formed on a sidewall of the dielectric structure, the insulating structure covers a first partial sidewall of the dielectric structure, and an air gap is formed between a second partial sidewall of the dielectric structure and the insulating structure; and forming a conductive structure, where the conductive structure covers an exposed pad and an outer sidewall surface of the insulating structure.