Patents Examined by Daniel Luke
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Patent number: 12112982Abstract: Methods for creating a conductive feature in a dielectric material are provided. In an embodiment, such a method comprises irradiating a region of a dielectric material having a resistivity of at least 108 W cm with a focused ion beam, the irradiated region corresponding to a conductive feature embedded in the dielectric material, the conductive feature having a conductivity greater than that of the dielectric material; and forming one or more contact pads of a conductive material in electrical communication with the conductive feature, the one or more contact pads configured to apply a voltage across the conductive feature using a voltage source.Type: GrantFiled: November 7, 2019Date of Patent: October 8, 2024Assignee: Northwestern UniversityInventors: Hooman Mohseni, Simone Bianconi
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Patent number: 12087719Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.Type: GrantFiled: February 12, 2021Date of Patent: September 10, 2024Assignee: Micron Technology, Inc.Inventors: Aibin Yu, Wei Zhou, Zhaohui Ma
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Patent number: 12087890Abstract: A light emitting device includes a light emitting element, a light-transmissive member, a bonding member and a light-reflective member. The bonding member is disposed between the light emitting element and the light-transmissive member, with the bonding member covering an upper surface of the light emitting element and at least a part of a lateral surface of the light emitting element. The light-reflective member covers the bonding member and a lateral surface of the light-transmissive member. The bonding member includes a surface that is flush with the lateral surface of the light-transmissive member, and an inclined surface that is inclined so as to extend toward the light-transmissive member.Type: GrantFiled: December 29, 2021Date of Patent: September 10, 2024Assignee: NICHIA CORPORATIONInventor: Rie Maeda
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Patent number: 12046506Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.Type: GrantFiled: July 22, 2021Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
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Patent number: 12046508Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids.Type: GrantFiled: February 10, 2023Date of Patent: July 23, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Shi You, He Ren, Naomi Yoshida, Nikolaos Bekiaris, Mehul Naik, Martin Jay Seamons, Jingmei Liang, Mei-Yee Shek
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Patent number: 12033927Abstract: A method for manufacturing a wiring substrate includes forming multiple conductor pads on an insulating layer such that the conductor pads include multiple first conductor pads and multiple second conductor pads, forming multiple protruding parts on surfaces of the first conductor pads of the conductor pads, respectively, forming a resin layer such that the resin layer covers the insulating layer and the conductor pads, exposing, from the resin layer, end portions of the protruding parts on the opposite side with respect to the insulating layer, forming, in the resin layer, multiple openings such that the openings expose surfaces of the second conductor pads of the conductor pads, respectively; and forming a coating film on the surfaces of the second conductor pads exposed in the openings.Type: GrantFiled: June 29, 2021Date of Patent: July 9, 2024Assignee: IBIDEN CO., LTD.Inventors: Isao Ohno, Tomoya Daizo, Yoji Sawada, Kazuhiko Kuranobu
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Patent number: 12009255Abstract: A method of manufacturing a semiconductor device comprises providing a substrate; forming an insulating layer on the substrate; etching the insulating layer to form an opening that exposes the substrate; forming a contact plug in the opening and on the insulating layer; forming a metal layer on the contact plug; and irradiating the metal layer with a laser.Type: GrantFiled: August 26, 2019Date of Patent: June 11, 2024Assignee: RNR LAB INC.Inventor: Jeong Do Ryu
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Patent number: 11984354Abstract: A method for forming a self-forming barrier in a feature of a substrate is provided, including the following operations: depositing a metallic liner in the feature of the substrate, the metallic liner being deposited over a dielectric of the substrate; depositing a zinc-containing precursor over the metallic liner; performing a thermal soak of the substrate; repeating the depositing of the zinc-containing precursor and the thermal soak of the substrate for a predefined number of cycles; wherein the method forms a zinc-containing barrier layer at an interface between the metallic liner and the dielectric.Type: GrantFiled: June 28, 2019Date of Patent: May 14, 2024Assignee: Lam Research CorporationInventors: Aniruddha Joi, Dries Dictus, Yezdi Dordi
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Patent number: 11978661Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.Type: GrantFiled: December 11, 2020Date of Patent: May 7, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Fuad H. Al-Amoody, Felix P. Anderson, Spencer H. Porter, Mark D. Levy, Siva P. Adusumilli
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Patent number: 11955379Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.Type: GrantFiled: September 15, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Wen Wu, Chun-I Tsai, Chi-Cheng Hung, Jyh-Cherng Sheu, Yu-Sheng Wang, Ming-Hsing Tsai
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Patent number: 11950458Abstract: A display apparatus includes a base substrate, a thin film transistor layer on the base substrate, an insulation layer on the thin film transistor layer, a first electrode on the insulation layer and in a light emitting area, a pixel defining layer having an opening that has a size and a shape substantially same as that of the first electrode, and on the insulation layer, a light emitting layer on the first electrode, and a second electrode on the light emitting layer.Type: GrantFiled: September 27, 2021Date of Patent: April 2, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: In Kyung Yoo, Donghyun Yang, SungBae Ju
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Patent number: 11929329Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.Type: GrantFiled: May 28, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Ming-Tsung Lee
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Patent number: 11923242Abstract: A method of manufacturing a semiconductor device, includes: stacking a thermally-decomposable organic material on a surface of a substrate in which a recess is formed; implanting ions into a surface of the organic material stacked in the recess so as to modify the surface of the organic material and form a modified layer on the surface of the organic material; and heating the substrate to a first temperature so as to thermally decompose the organic material under the modified layer and to desorb the organic material through the modified layer so that an air gap is formed between the modified layer and the recess.Type: GrantFiled: April 8, 2021Date of Patent: March 5, 2024Assignee: Tokyo Electron LimitedInventors: Tatsuya Yamaguchi, Syuji Nozawa
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Patent number: 11923291Abstract: A semiconductor device includes a first substrate, a logical circuit, a first insulating film, a wiring, a plug, and a first layer containing a metal oxide or a metal nitride. The logical circuit is disposed on the first substrate. The first insulating film is disposed above the logical circuit. The wiring includes a first film disposed in the first insulating film, the first film extending in a first direction along an upper surface of the first substrate, and the first film containing a metal, and a first metal layer disposed in the first insulating film via the first film. The plug is disposed under the wiring, extends in a second direction that intersects the first direction, and is electrically connected to the wiring. The first layer is provided between an upper end of the plug and a bottom end of the wiring.Type: GrantFiled: August 31, 2020Date of Patent: March 5, 2024Assignee: KIOXIA CORPORATIONInventor: Atsushi Kato
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Patent number: 11901220Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.Type: GrantFiled: July 23, 2020Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
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Patent number: 11894322Abstract: Radio frequency integrated device packages having bump and/or ball launch structures are disclosed herein. The bump launch structures can comprise patterned metallic and insulating material that substantially matches the impedance of a radio frequency integrated device die. The ball launch structures can comprise patterned metallic and insulating material that substantially matches the impedance of a system board.Type: GrantFiled: May 23, 2019Date of Patent: February 6, 2024Assignee: Analog Devices, Inc.Inventor: Bruce E. Wilcox
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Patent number: 11894264Abstract: The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.Type: GrantFiled: April 8, 2022Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11791204Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.Type: GrantFiled: February 9, 2021Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11784258Abstract: A thin film transistor, a manufacturing method thereof, an array substrate, and a display device are provided. The thin film transistor comprises a base substrate, a gate on the base substrate, a gate insulating layer covering the gate, an active layer on the gate insulating layer, a first electrode and a second electrode over and electrically connected to the active layer, and a first insulating portion between the gate insulating layer and the first electrode. An orthographic projection of the first insulating portion on the base substrate, an orthographic projection of the first electrode on the base substrate, and an orthographic projection of a boundary between a side surface of the gate and an upper surface of the gate on the base substrate at least partially overlap.Type: GrantFiled: April 4, 2018Date of Patent: October 10, 2023Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Kuhyun Park
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Patent number: 11758761Abstract: An organic light emitting display device includes: a substrate; a first electrode on the substrate; a pixel defining layer on the substrate, the pixel defining layer defining a first opening which exposes at least a part of the first electrode; an organic light emitting layer on the first electrode; a second electrode on the organic light emitting layer; a thin film encapsulation layer on the second electrode; a sensing electrode on the thin film encapsulation layer; a low refractive index layer on the sensing electrode, the low refractive index layer defining a second opening which overlaps the first opening; and a high refractive index layer on the thin film encapsulation layer. A gap between an edge of the first opening and an edge of the second opening is constant irrespective of direction.Type: GrantFiled: May 6, 2020Date of Patent: September 12, 2023Assignee: Samsung Display Co., Ltd.Inventors: Soonil Jung, Haeyoung Yun, Junghyun Cho, Sanghyun Choi