Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.

Abstract: The present disclosure provides an organic light emitting diode and method for manufacturing the same. The organic light emitting diode includes a substrate; an anode layer formed on a substrate, a hole transmission layer formed on the anode layer, a hole transmission auxiliary layer formed on the hole transmission layer and performed by a photolithography process, wherein the hole transmission auxiliary layer protects a surface of the hole transmission layer, at least one illuminating block formed on the hole transmission auxiliary layer, wherein the hole transmission auxiliary layer is electrically connected between the at least one illuminating block and the hole transmission layer, an electron transmission auxiliary layer formed on the at least one illuminating block; an electron transmission layer formed on the electron transmission auxiliary layer and a cathode layer formed on the electron transmission layer.

Abstract: The method of manufacturing a light emitting device includes: providing a light-transmissive member having a plate-like shape; providing light emitting elements each having a primary light emission surface and an electrode formation surface; bonding the light emitting elements to a base member such that the electrode formation surfaces of the light emitting elements face an upper surface of the base member; disposing the light emitting elements on the light-transmissive member such that the primary light emission surfaces of the light emitting elements face an upper surface of the light-transmissive member via a light-transmissive bonding member; disposing a part of the bonding member on a lateral surface of each of the light emitting elements; removing a part of the light-transmissive member to form a groove between the light emitting elements; forming a light-reflective member at least in the groove; and cutting the light-reflective member and the base member.

Abstract: An organic light emitting display device includes: a substrate; a first electrode on the substrate; a pixel defining layer on the substrate, the pixel defining layer defining a first opening which exposes at least a part of the first electrode; an organic light emitting layer on the first electrode; a second electrode on the organic light emitting layer; a thin film encapsulation layer on the second electrode; a sensing electrode on the thin film encapsulation layer; a low refractive index layer on the sensing electrode, the low refractive index layer defining a second opening which overlaps the first opening; and a high refractive index layer on the thin film encapsulation layer. A gap between an edge of the first opening and an edge of the second opening is constant irrespective of direction.

Abstract: A memory package includes a plurality of memory chips stacked on a package substrate. A logic chip is disposed between the plurality of memory chips and the package substrate. The logic chip is configured to control the plurality of memory chips through a plurality of vias passing through the plurality of memory chips. An intermediate chip is connected to the plurality of vias. The intermediate chip is disposed between the plurality of memory chips and the logic chip, and is configured to select at least a subset of the plurality of vias as a data transmission path between the logic chip and the plurality of memory chips, based on a data transmission rate of the logic chip.

Abstract: One embodiment of the invention relates to a method for fabricating a doped semiconductor zone in a semiconductor body. The method includes implanting dopant particles via one side into the semiconductor body or applying a layer containing dopant particles to one side of the semiconductor body. The method also includes irradiating the semiconductor body via the one side with further particles at least in the region containing the dopant particles. The method finally includes carrying out a thermal treatment by means of which the semiconductor body is heated, at least in the region containing the dopant particles, to a predetermined temperature in order to activate the implanted dopant particles, said temperature being less than 700° C.

Abstract: A light emitting device includes a light emitting element; a light-transmissive member that has a lower surface positioned inside a peripheral edge of an upper surface of the light emitting element in plan view, a first lateral surface extending from the lower surface and having at least one inclined surface that is inclined with respect to the upper surface of the light emitting element, and a second lateral surface positioned above and outside the first lateral surface; a light-transmissive adhesive member positioned inside the second lateral surface in plan view, wherein the adhesive member adheres the upper surface of the light emitting element and the lower surface of the light-transmissive member to each other and covers the first lateral surface; and a light-reflective member covering the second lateral surface.

Abstract: A display device is provided including a plurality of pixels, wherein the plurality of pixels is arranged in a matrix form, wherein each of the plurality of pixels has an emission region and a transparent region, and wherein the emission region has a light-emitting element, and the transparent region has at least a part of a storage capacitor having transparency and is covered with at least one electrode of the storage capacitor, a first electrode covers the plurality of pixels, a light-emitting layer is arranged below the first electrode, a second electrode is arranged below the light-emitting layer, and the storage capacitor includes the first electrode.

Abstract: In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.

Abstract: A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Abstract: A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

Abstract: A nitride-based Schottky diode includes a nitride-based semiconductor body, a first metal layer forming the anode electrode, a cathode electrode in electrical contact with the nitride-based semiconductor body, and a termination structure including a guard ring and a dielectric field plate. In one embodiment, the cathode electrode is formed on the front side of the nitride-based semiconductor body, in an area away from the anode electrode and the termination structure. In another embodiment, the dielectric field plate includes a first dielectric layer and a recessed second dielectric layer. In another embodiment, the dielectric field plate and the nitride-based epitaxial layer are formed with a slant profile at a side facing the Schottky junction of the Schottky diode. In another embodiment, the dielectric field plate is formed on a top surface of the nitride-based epitaxial layer and recessed from an end of the nitride-based epitaxial layer near the Schottky junction.

Abstract: Aspects of the disclosure provide a waterproof packaging technique for fabricating waterproof microphones in mobile devices. A device based on the waterproof packaging technique can include a microelectromechanical system (MEMS) device, a housing enclosing the MEMS device, and a liquid-resistant air inlet passive device (LRAPD) on the housing. The LRAPD can include at least one channel connecting an exterior of the housing with a chamber formed between the housing and the MEMS device. An inside surface of the channel can be coated with a liquid-repellant coating. In some examples, the liquid-repellant coating can be a self-assembled monolayer (SAM) coating.

Abstract: A display device is provided including a plurality of pixels, wherein the plurality of pixels is arranged in a matrix form, wherein each of the plurality of pixels has an emission region and a transparent region, and wherein the emission region has a light-emitting element, and the transparent region has at least a part of a storage capacitor having transparency and is covered with at least one electrode of the storage capacitor, a first electrode covers the plurality of pixels, a light-emitting layer is arranged below the first electrode, a second electrode is arranged below the light-emitting layer, and the storage capacitor includes the first electrode.

Abstract: A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.

Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.

Abstract: A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

Abstract: A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.