Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

Abstract: Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

Abstract: A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

Abstract: Provided is an electronic device including a first electrode; a second electrode facing the first electrode; and an active layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a first surface that is closest to the active layer and a second surface that is farthest from the active layer, a size of a cross-sectional horizontal area at the first surface is smaller than a size of a cross-sectional horizontal area at the second surface, the active layer includes a first region, which vertically overlaps the first surface, and a second region outside the first region, and a thickness of the active layer in the first region is smaller than a thickness of the active layer in the second region.

Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.

Abstract: A light emitting device including a substrate having a first surface and a second surface opposing each other, a plurality of light emitting parts disposed on the first surface of the substrate and defining a light emitting area, and a light shielding layer disposed on the second surface of the substrate and exposing at least a portion of the light emitting area, in which the light shielding layer has a thickness greater than a length of the longest wavelength among wavelengths of light generated from the light emitting parts.

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

Abstract: A method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

Abstract: A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.

Abstract: In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate and a conductive layer, in which the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer includes one or more first trace. The first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed on the one or more first trace and in the recess.

Abstract: A method of producing an electroconductive substrate including a base material, and an electroconductive pattern disposed on one main surface side of the base material includes: a step of forming a trench including a bottom surface to which a foundation layer is exposed, and a lateral surface which includes a surface of a trench formation layer, according to an imprint method; and a step of forming an electroconductive pattern layer by growing metal plating from the foundation layer which is exposed to the bottom surface of the trench.

Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

Abstract: A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

Abstract: Aspects of the disclosure provide a waterproof packaging technique for fabricating waterproof microphones in mobile devices. A device based on the waterproof packaging technique can include a microelectromechanical system (MEMS) device, a housing enclosing the MEMS device, and a liquid-resistant air inlet passive device (LRAPD) on the housing. The LRAPD can include at least one channel connecting an exterior of the housing with a chamber formed between the housing and the MEMS device. An inside surface of the channel can be coated with a liquid-repellant coating. In some examples, the liquid-repellant coating can be a self-assembled monolayer (SAM) coating.

Abstract: A display device is provided including a plurality of pixels, wherein the plurality of pixels is arranged in a matrix form, wherein each of the plurality of pixels has an emission region and a transparent region, and wherein the emission region has a light-emitting element, and the transparent region has at least a part of a storage capacitor having transparency and is covered with at least one electrode of the storage capacitor, a first electrode covers the plurality of pixels, a light-emitting layer is arranged below the first electrode, a second electrode is arranged below the light-emitting layer, and the storage capacitor includes the first electrode.