Patents Examined by Daniel McMahon
  • Patent number: 10270467
    Abstract: Provided is a signal interleaving method which includes: interleaving parity bits by encoding input bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800; splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups; interleaving the plurality of bit groups according to a specific permutation order to provide an interleaved codeword; de-multiplexing bits of the interleaved codeword to generate data cells; mapping the data cells onto constellation points for 1024-quadrature amplitude modulation (QAM); and transmitting a signal based on the constellation points.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-Joong Kim, Se-ho Myung
  • Patent number: 10191112
    Abstract: Disclosed are embodiments of a method that provides for pre-production run development of a fail signature database, which stores fail signatures for systematic defects and corresponding root causes. The fail signatures in the database is subsequently accessed and used for a variety of purposes. For example, the fail signatures are evaluated and, based on the results of the evaluation, actions are taken to prevent specific systematic defects from occurring during production runs and/or to allow for early detection of specific systematic defects during production runs. In some embodiments, following production runs, new fail signatures from failing production chips are developed and compared against the fail signatures in the fail signature database. In some embodiments, when a signature match indicates that a particular production chip has a same systematic defect with a same root cause as a particular prototype chip in-line advanced process control (APC) is performed.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rao Desineni, Atul Chittora, Yan Pan, Sherwin Fernandes, Thomas Herrmann
  • Patent number: 10140176
    Abstract: An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanguhn Cha, Hoiju Chung, Uksong Kang, Chulwoo Park
  • Patent number: 10142056
    Abstract: In a transmission method according to one aspect of the present disclosure, a cyclic shift is applied to each row of an interleaver matrix in which each of a plurality of rotation components of each section is replaced with a cell, in which two rotation components are set to a real component and an imaginary component, by using (cyclic shift value k×floor(Q/max{D,(NRF×NC)}/2)) cells allocated to the row, and a value of k mod NRF varies in at least two rows of one section portion of a combined complex interleaver matrix in the cyclic shift.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 27, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Peter Klenner, Mikihiro Ouchi
  • Patent number: 10122384
    Abstract: Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: November 6, 2018
    Assignee: ARM Limited
    Inventors: Liangzhen Lai, Vikas Chandra, Gary Dale Carpenter
  • Patent number: 10120599
    Abstract: In one embodiment, a method includes reading a plurality of narrow-spread (NS) codewords from M tracks of a magnetic tape medium using a plurality of read elements, the plurality of NS codewords collectively comprising data logically organized as a predetermined number of two-dimensional arrays. Each two-dimensional array includes a predetermined number of NS codewords positioned orthogonally to a predetermined number of wide-spread (WS) codewords, with a first NS codeword from a first two-dimensional array being read in its entirety from the magnetic tape medium prior to reading a second NS codeword from the first two-dimensional array. The method also includes laterally decoding each NS codeword from the first two-dimensional array read from the M tracks of the magnetic tape medium in succession prior to decoding any WS codewords from the first two-dimensional array. The NS codewords are protected with a stronger encoding than the WS codewords within each two-dimensional array.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roy D. Cideciyan, Simeon Furrer, Ernest S. Gale, Mark A. Lantz
  • Patent number: 10115479
    Abstract: A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jung Kim, Young-Uk Chang
  • Patent number: 10108485
    Abstract: A method for automatic correction of nonvolatile memory in information handling systems includes storing ECC data for a compressed BIOS firmware. The ECC data are used to identify and correct error bits in the compressed BIOS firmware. The discovered error bits are recorded in the nonvolatile memory and accessed for a faster correction method for the compressed BIOS firmware than using the ECC data on subsequent attempts.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: October 23, 2018
    Assignee: Dell Products L.P.
    Inventors: Craig Lawrence Chaiken, Balasingh Ponraj Samuel, Anand Prakash Joshi
  • Patent number: 10101387
    Abstract: An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via multiple logic signals. The JTAG system includes a JTAG interface receives the multiple logic signals. The JTAG system also includes a JTAG hub instantiated in the first partition and being communicatively coupled to the JTAG interface. The JTAG system further includes JTAG-based logic instantiated in the second partition. The integrated circuit device further includes an interface instantiated in the first partition configured to communicatively couple the JTAG hub to the JTAG-based logic.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Mahesh A. Iyer, Yi Peng
  • Patent number: 10097311
    Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 10090044
    Abstract: A memory system can program data in different modes, such as normal mode programming and burst mode programming. Burst mode programming programs data into the memory device faster than normal mode programming. MLC Blocks for burst mode programming are selected based on one or more criteria, such as block age, block programming speed, or the like. Further, one or more burst mode TRIM settings, which include one or more of a program voltage TRIM setting, a step-up voltage TRIM setting, skip verify level, and a program pulse width, are used to program the blocks selected for burst mode programming. In this regard, burst mode programming is performed more quickly than normal mode programming.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: October 2, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Stella Achtenberg, Alon Eyal, Eran Sharon
  • Patent number: 10088526
    Abstract: A tester for integrated circuits on a silicon wafer includes an input/output connection for testing an integrated circuit. The tester comprises circuitry arranged for transferring a first data frame to the integrated circuit via the input/output connection, the first data frame including a time reference for the data included in the data frame, a field for validating the time reference and a data field including at least one test command and for receiving a second data frame via the input/output connection, the data in the second data frame received having a duration that is a multiple of the time reference.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 2, 2018
    Assignee: STARCHIP
    Inventors: Cyrille Lambert, Sébastien Bayon, Alexandre Croguennec
  • Patent number: 10090858
    Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwon Cho, Hynsoo Bae, Hyotaek Leem, Dong-Ryoul Lee, Hyun Ju Yi, Taehack Lee
  • Patent number: 10084484
    Abstract: A storage control apparatus obtains first-code attached data, each having target data to be written and first code information, which includes an error detection code based on the target data and information about a first write destination, attached to the target data. The storage control apparatus then obtains the target data by excluding the first code information from the first-code attached data eliminates duplication of the target data, generates second code information which includes an error detection code for the target data remaining and information about a second write destination, and writes second-code attached data including the second code information into a memory device.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 25, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Katsuhiko Nagashima
  • Patent number: 10078547
    Abstract: Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond Wong, Jie Zheng
  • Patent number: 10073658
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request involving a set of EDSs associated with a data object that are distributedly stored among storage units (SUs) including first SU(s) coupled via a local network of the DSN and second SU(s) remotely located to the computing device and coupled via an external network of the DSN. The computing device caches within the at least one memory therein a subset of EDSs stored within the second SU(s) remotely located to the computing device and coupled to the computing device via the external network.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manish Motwani, Ethan S. Wozniak
  • Patent number: 10073138
    Abstract: An apparatus is described that includes a plurality of circuits each designed to exhibit a unique signature code that is determined from manufacturing tolerances associated with a manufacturing process used to manufacture the circuits. The apparatus also includes error circuitry to determine an error has arisen based on a change in signature codes from the plurality of circuits.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Suraj Sindia, Robert Kwasnick, Dhruv Singh
  • Patent number: 10075191
    Abstract: The invention relates to a method for decoding read bits including information bits from memory cells of a solid-state drive. The method comprises providing an indication of reliability of the read bits, and, based on the indication of reliability, iteratively soft decoding the read bits in order to obtain the information bits, wherein the soft decoding comprises, at each iteration of the soft decoding, if the current number of iterations has reached a predetermined number of iterations indicative of an admitted latency of the solid state drive, and if no information bits having an error rate below a predetermined error rate have been obtained, providing a further indication of reliability of the read bits, and iteratively soft decoding the read bits based on the further indication of reliability. The invention also relates to a corresponding controller and a corresponding solid-state drive.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 11, 2018
    Assignee: NandEXT Srl
    Inventor: Margherita Maffeis
  • Patent number: 10063257
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10063259
    Abstract: An interleaving method and apparatus for adaptively determining an interleaving depth of each of one or more interleaving blocks based on a maximum interleaving depth and a number of codewords of a packet, and interleaving the interleaving blocks based on the interleaving depth. The adaptively determining the interleaving depth includes: calculating a number of remaining codewords by performing a modulo operation on a basic interleaving depth and the number of the codewords; and determining the interleaving depth by adjusting the basic interleaving depth based on the number of the remaining codewords.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaewook Shim, Chang Soon Park